JPS554741A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS554741A
JPS554741A JP7711778A JP7711778A JPS554741A JP S554741 A JPS554741 A JP S554741A JP 7711778 A JP7711778 A JP 7711778A JP 7711778 A JP7711778 A JP 7711778A JP S554741 A JPS554741 A JP S554741A
Authority
JP
Japan
Prior art keywords
logical
integrated circuit
true
blocks
become
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7711778A
Other languages
Japanese (ja)
Inventor
Hideo Kikuchi
Shigeto Koda
Shigenobu Sakai
Yoshitaka Kitano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP7711778A priority Critical patent/JPS554741A/en
Publication of JPS554741A publication Critical patent/JPS554741A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE: To obtain surely only a true value as a logical output by controlling the turning-on and off of a switching element according to true and false signals outputted from an integrated circuit which sends the logical output.
CONSTITUTION: Integrated circuit blocks 31, 32, etc., generate binary logical outputs and true and false signals of logic 0 and 1, which indicate that signals are ture or false, according to partial defects at a production time, etc. Consequently, when logical outputs of blocks 31 and 32 are false signals, transistors 37 and 38 become conductive, and logical output of blocks 31 and 32 become a reference potential forcedly and become logical 0, and only true values are surely obtained as a logical output by OR of logical operation circuit 39 formed by an OR circuit.
COPYRIGHT: (C)1980,JPO&Japio
JP7711778A 1978-06-23 1978-06-23 Semiconductor integrated circuit Pending JPS554741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7711778A JPS554741A (en) 1978-06-23 1978-06-23 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7711778A JPS554741A (en) 1978-06-23 1978-06-23 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS554741A true JPS554741A (en) 1980-01-14

Family

ID=13624836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7711778A Pending JPS554741A (en) 1978-06-23 1978-06-23 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS554741A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860489A (en) * 1981-10-06 1983-04-09 Nippon Telegr & Teleph Corp <Ntt> Memory circuit
US4803636A (en) * 1985-09-27 1989-02-07 Hitachi Ltd. Circuit translator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869439A (en) * 1971-12-21 1973-09-20
JPS51146127A (en) * 1975-06-11 1976-12-15 Hitachi Ltd Memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869439A (en) * 1971-12-21 1973-09-20
JPS51146127A (en) * 1975-06-11 1976-12-15 Hitachi Ltd Memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860489A (en) * 1981-10-06 1983-04-09 Nippon Telegr & Teleph Corp <Ntt> Memory circuit
US4803636A (en) * 1985-09-27 1989-02-07 Hitachi Ltd. Circuit translator

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