JPS5540787Y2 - - Google Patents
Info
- Publication number
- JPS5540787Y2 JPS5540787Y2 JP13146175U JP13146175U JPS5540787Y2 JP S5540787 Y2 JPS5540787 Y2 JP S5540787Y2 JP 13146175 U JP13146175 U JP 13146175U JP 13146175 U JP13146175 U JP 13146175U JP S5540787 Y2 JPS5540787 Y2 JP S5540787Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Insertion, Bundling And Securing Of Wires For Electric Apparatuses (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13146175U JPS5540787Y2 (en:Method) | 1975-09-25 | 1975-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13146175U JPS5540787Y2 (en:Method) | 1975-09-25 | 1975-09-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5244366U JPS5244366U (en:Method) | 1977-03-29 |
| JPS5540787Y2 true JPS5540787Y2 (en:Method) | 1980-09-24 |
Family
ID=28611620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13146175U Expired JPS5540787Y2 (en:Method) | 1975-09-25 | 1975-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5540787Y2 (en:Method) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54178933U (en:Method) * | 1978-06-07 | 1979-12-18 | ||
| JPS5734309Y2 (en:Method) * | 1978-07-29 | 1982-07-28 | ||
| JPS5943759Y2 (ja) * | 1979-06-20 | 1984-12-26 | パイオニア株式会社 | フレキシブル基板による線処理装置 |
-
1975
- 1975-09-25 JP JP13146175U patent/JPS5540787Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5244366U (en:Method) | 1977-03-29 |