JPS5539980A - Urgent control circuit - Google Patents

Urgent control circuit

Info

Publication number
JPS5539980A
JPS5539980A JP11300878A JP11300878A JPS5539980A JP S5539980 A JPS5539980 A JP S5539980A JP 11300878 A JP11300878 A JP 11300878A JP 11300878 A JP11300878 A JP 11300878A JP S5539980 A JPS5539980 A JP S5539980A
Authority
JP
Japan
Prior art keywords
circuit
present
output
signal
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11300878A
Other languages
Japanese (ja)
Other versions
JPS603220B2 (en
Inventor
Tetsuo Urushibara
Yuichi Morikawa
Hideyuki Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP53113008A priority Critical patent/JPS603220B2/en
Publication of JPS5539980A publication Critical patent/JPS5539980A/en
Publication of JPS603220B2 publication Critical patent/JPS603220B2/en
Expired legal-status Critical Current

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Abstract

PURPOSE: To simplify the construction and the control and enhance the reliability by providing in two sets of center processing device perliminarily constructed at present an abnormality detection circuit and a gate circuit having a double stabilizing circuit in distribution.
CONSTITUTION: When one center processing device CC1 is used at present and the other one CC2 is used for perliminary one, the present and preliminary signal ms 1 is 0, and ms 2 is 1. When the abnormal condition of the CC1 is detected by the system abnormal detection circuit DET1, the output signal thereof is 0 and the initiation signal st1 is 1 and ms1 is 1. Thus, the double stabilizing circuit comprising NAND circuits N 11, N 21 is inverted and ms 2 is 0 and the CC2 of the present use is indicated and the output of NAND circuit N22 is 1 and the initiation signal st 2 of the output of the OR circuit OR 2 is 1 to carry out the urgent control operation.
COPYRIGHT: (C)1980,JPO&Japio
JP53113008A 1978-09-14 1978-09-14 emergency control circuit Expired JPS603220B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53113008A JPS603220B2 (en) 1978-09-14 1978-09-14 emergency control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53113008A JPS603220B2 (en) 1978-09-14 1978-09-14 emergency control circuit

Publications (2)

Publication Number Publication Date
JPS5539980A true JPS5539980A (en) 1980-03-21
JPS603220B2 JPS603220B2 (en) 1985-01-26

Family

ID=14601117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53113008A Expired JPS603220B2 (en) 1978-09-14 1978-09-14 emergency control circuit

Country Status (1)

Country Link
JP (1) JPS603220B2 (en)

Also Published As

Publication number Publication date
JPS603220B2 (en) 1985-01-26

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