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Priority claimed from FR7239747Aexternal-prioritypatent/FR2205800B1/fr
Application filedfiledCritical
Publication of JPS49133867ApublicationCriticalpatent/JPS49133867A/ja
Publication of JPS5537868B2publicationCriticalpatent/JPS5537868B2/ja
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
H01L2224/93—Batch processes
H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Electric Connection Of Electric Components To Printed Circuits
(AREA)
