JPS5535508A - Bright line erasing signal generating circuit at channel switch-over time - Google Patents

Bright line erasing signal generating circuit at channel switch-over time

Info

Publication number
JPS5535508A
JPS5535508A JP10813878A JP10813878A JPS5535508A JP S5535508 A JPS5535508 A JP S5535508A JP 10813878 A JP10813878 A JP 10813878A JP 10813878 A JP10813878 A JP 10813878A JP S5535508 A JPS5535508 A JP S5535508A
Authority
JP
Japan
Prior art keywords
signal
bright line
flop
flip
fly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10813878A
Other languages
Japanese (ja)
Inventor
Fumio Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10813878A priority Critical patent/JPS5535508A/en
Publication of JPS5535508A publication Critical patent/JPS5535508A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To switch over the contents of a picture extremely clearly at channel switch-over time causing operation start and termination of bright line erasing in the middle of channel change-over to coincide with a fly-back time of a vertical deflection circuit.
CONSTITUTION: When a detection signal a that a station select button was pushed respectively and a vertical fly-back pulse b are applied from terminals 1, 2, a flip- flop 2 is set by the signal a, and a monostable multibivrator 5 rises up synchronized with the vertical fly-back pulse b to issue an output signal e. At the same time, the flip-flop 3 is reset. By fall of the signal e, a flip-flop 6 is set, and reset by the first vertical fly-back pulse after that. A logical sum output h of the signal e and the output f of the flip-flop 6 being what synchronized with the vertical fly-back pulse b, this output h is used as the bright line erasing signal. Also, station select operation is implemented between time t1 and t2.
COPYRIGHT: (C)1980,JPO&Japio
JP10813878A 1978-09-05 1978-09-05 Bright line erasing signal generating circuit at channel switch-over time Pending JPS5535508A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10813878A JPS5535508A (en) 1978-09-05 1978-09-05 Bright line erasing signal generating circuit at channel switch-over time

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10813878A JPS5535508A (en) 1978-09-05 1978-09-05 Bright line erasing signal generating circuit at channel switch-over time

Publications (1)

Publication Number Publication Date
JPS5535508A true JPS5535508A (en) 1980-03-12

Family

ID=14476891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10813878A Pending JPS5535508A (en) 1978-09-05 1978-09-05 Bright line erasing signal generating circuit at channel switch-over time

Country Status (1)

Country Link
JP (1) JPS5535508A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59153387A (en) * 1983-02-21 1984-09-01 Sony Corp Channel selecting circuit
JPH04176277A (en) * 1990-11-09 1992-06-23 Matsushita Electric Ind Co Ltd Picture mute circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59153387A (en) * 1983-02-21 1984-09-01 Sony Corp Channel selecting circuit
JPH04176277A (en) * 1990-11-09 1992-06-23 Matsushita Electric Ind Co Ltd Picture mute circuit

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