JPS553483U - - Google Patents

Info

Publication number
JPS553483U
JPS553483U JP5668879U JP5668879U JPS553483U JP S553483 U JPS553483 U JP S553483U JP 5668879 U JP5668879 U JP 5668879U JP 5668879 U JP5668879 U JP 5668879U JP S553483 U JPS553483 U JP S553483U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5668879U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5668879U priority Critical patent/JPS553483U/ja
Publication of JPS553483U publication Critical patent/JPS553483U/ja
Pending legal-status Critical Current

Links

JP5668879U 1979-04-26 1979-04-26 Pending JPS553483U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5668879U JPS553483U (en) 1979-04-26 1979-04-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5668879U JPS553483U (en) 1979-04-26 1979-04-26

Publications (1)

Publication Number Publication Date
JPS553483U true JPS553483U (en) 1980-01-10

Family

ID=28953831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5668879U Pending JPS553483U (en) 1979-04-26 1979-04-26

Country Status (1)

Country Link
JP (1) JPS553483U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3281805A (en) * 1962-10-11 1966-10-25 Itt Skew elimination system utilizing a plurality of buffer shift registers

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3281805A (en) * 1962-10-11 1966-10-25 Itt Skew elimination system utilizing a plurality of buffer shift registers

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