JPS5531822Y2 - - Google Patents

Info

Publication number
JPS5531822Y2
JPS5531822Y2 JP1974147854U JP14785474U JPS5531822Y2 JP S5531822 Y2 JPS5531822 Y2 JP S5531822Y2 JP 1974147854 U JP1974147854 U JP 1974147854U JP 14785474 U JP14785474 U JP 14785474U JP S5531822 Y2 JPS5531822 Y2 JP S5531822Y2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1974147854U
Other languages
Japanese (ja)
Other versions
JPS5173973U (enrdf_load_html_response
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1974147854U priority Critical patent/JPS5531822Y2/ja
Publication of JPS5173973U publication Critical patent/JPS5173973U/ja
Application granted granted Critical
Publication of JPS5531822Y2 publication Critical patent/JPS5531822Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1974147854U 1974-12-05 1974-12-05 Expired JPS5531822Y2 (enrdf_load_html_response)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1974147854U JPS5531822Y2 (enrdf_load_html_response) 1974-12-05 1974-12-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1974147854U JPS5531822Y2 (enrdf_load_html_response) 1974-12-05 1974-12-05

Publications (2)

Publication Number Publication Date
JPS5173973U JPS5173973U (enrdf_load_html_response) 1976-06-10
JPS5531822Y2 true JPS5531822Y2 (enrdf_load_html_response) 1980-07-29

Family

ID=28438961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1974147854U Expired JPS5531822Y2 (enrdf_load_html_response) 1974-12-05 1974-12-05

Country Status (1)

Country Link
JP (1) JPS5531822Y2 (enrdf_load_html_response)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5756512Y2 (enrdf_load_html_response) * 1975-12-18 1982-12-04
JPS6098652A (ja) * 1983-11-02 1985-06-01 Mitsubishi Electric Corp 半導体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS568017B2 (enrdf_load_html_response) * 1972-06-02 1981-02-20

Also Published As

Publication number Publication date
JPS5173973U (enrdf_load_html_response) 1976-06-10

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