JPS5531354A - Muting circuit for audio device - Google Patents

Muting circuit for audio device

Info

Publication number
JPS5531354A
JPS5531354A JP10473178A JP10473178A JPS5531354A JP S5531354 A JPS5531354 A JP S5531354A JP 10473178 A JP10473178 A JP 10473178A JP 10473178 A JP10473178 A JP 10473178A JP S5531354 A JPS5531354 A JP S5531354A
Authority
JP
Japan
Prior art keywords
positive
muting
input signal
negative
pnp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10473178A
Other languages
Japanese (ja)
Other versions
JPS5925496B2 (en
Inventor
Noriyuki Sasaki
Kosaku Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marantz Japan Inc
Original Assignee
Marantz Japan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marantz Japan Inc filed Critical Marantz Japan Inc
Priority to JP10473178A priority Critical patent/JPS5925496B2/en
Publication of JPS5531354A publication Critical patent/JPS5531354A/en
Publication of JPS5925496B2 publication Critical patent/JPS5925496B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/34—Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems

Landscapes

  • Noise Elimination (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To obtain the sufficient muting effect to both the positive and negative input pulse by applying both the NPN- and PNP-type transistors to control the input signal at the input signal line to the main amplifier. CONSTITUTION:The signals branched off from input signal line 1 are supplied to the collector to which NPN- and PNP-type transistors Tr2 and 3 are connected in common. The emitters of Tr2 and 3 are grounded. Furthermore the anode of Zener diode 4 is connected to the base of Tr2; the cathode of Zener diode 7 is connected to the base of Tr3; the other end of diodes 4 and 7 each is connected to the emitter and the collector of driving Tr5; and both the positive and negative voltage of DC voltage are applied to the bases of Tr2 and 3 each. And when the muting control signal features zero. Tr5 is cut off by the discharge current of the delay circuit with application of the forward bias to the bases of Tr2 and 3. Thus the conduction is secured for both Tr2 and 3, ensuring an effective muting to both the positive and negative pulses.
JP10473178A 1978-08-28 1978-08-28 Muting circuit in audio equipment Expired JPS5925496B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10473178A JPS5925496B2 (en) 1978-08-28 1978-08-28 Muting circuit in audio equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10473178A JPS5925496B2 (en) 1978-08-28 1978-08-28 Muting circuit in audio equipment

Publications (2)

Publication Number Publication Date
JPS5531354A true JPS5531354A (en) 1980-03-05
JPS5925496B2 JPS5925496B2 (en) 1984-06-18

Family

ID=14388634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10473178A Expired JPS5925496B2 (en) 1978-08-28 1978-08-28 Muting circuit in audio equipment

Country Status (1)

Country Link
JP (1) JPS5925496B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58121436U (en) * 1982-02-12 1983-08-18 株式会社ケンウッド switching circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123469U (en) * 1991-04-17 1992-11-09 純一郎 村上 Golf player progress monitoring device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58121436U (en) * 1982-02-12 1983-08-18 株式会社ケンウッド switching circuit

Also Published As

Publication number Publication date
JPS5925496B2 (en) 1984-06-18

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