JPS553082A - Control system for memory device - Google Patents

Control system for memory device

Info

Publication number
JPS553082A
JPS553082A JP7615878A JP7615878A JPS553082A JP S553082 A JPS553082 A JP S553082A JP 7615878 A JP7615878 A JP 7615878A JP 7615878 A JP7615878 A JP 7615878A JP S553082 A JPS553082 A JP S553082A
Authority
JP
Japan
Prior art keywords
computer
memory
memory medium
medium
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7615878A
Other languages
Japanese (ja)
Inventor
Yoshiji Fukai
Norio Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Yokogawa Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp, Yokogawa Electric Works Ltd filed Critical Yokogawa Hokushin Electric Corp
Priority to JP7615878A priority Critical patent/JPS553082A/en
Publication of JPS553082A publication Critical patent/JPS553082A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To avoid the overrun of the memory medium in case the computer is combined with the medium rotary-type memory device featuring a higher speed than the operation speed of the computer, by performing the address distribution for the memory medium in accordance with the process time of the computer.
CONSTITUTION: Memory device 3 features a higher speed than the operation of computer 1 and possesses the memory medium featuring the substantially endless turns. Control unit 2 controls the data transfer between computer 1 and device 3. In this case, the access is given at intervals and with a proper space corresponding to the process time of each block computer of the memory medium. At the same time, first-in/first-out memory 201 is installed between computer 1 and device 3 as the data transfer buffer, and thus the data is transferred through memory 201 with every block of the memory medium. As a result, the overrun can be prevented with a highly efficient use of the memory device secured.
COPYRIGHT: (C)1980,JPO&Japio
JP7615878A 1978-06-23 1978-06-23 Control system for memory device Pending JPS553082A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7615878A JPS553082A (en) 1978-06-23 1978-06-23 Control system for memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7615878A JPS553082A (en) 1978-06-23 1978-06-23 Control system for memory device

Publications (1)

Publication Number Publication Date
JPS553082A true JPS553082A (en) 1980-01-10

Family

ID=13597234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7615878A Pending JPS553082A (en) 1978-06-23 1978-06-23 Control system for memory device

Country Status (1)

Country Link
JP (1) JPS553082A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4882811A (en) * 1972-02-04 1973-11-06
JPS4975233A (en) * 1972-11-22 1974-07-19

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4882811A (en) * 1972-02-04 1973-11-06
JPS4975233A (en) * 1972-11-22 1974-07-19

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