JPS5523576A - Erroneous output prevention system - Google Patents

Erroneous output prevention system

Info

Publication number
JPS5523576A
JPS5523576A JP9653678A JP9653678A JPS5523576A JP S5523576 A JPS5523576 A JP S5523576A JP 9653678 A JP9653678 A JP 9653678A JP 9653678 A JP9653678 A JP 9653678A JP S5523576 A JPS5523576 A JP S5523576A
Authority
JP
Japan
Prior art keywords
unit
prevention system
voltages
established
transmitted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9653678A
Other languages
Japanese (ja)
Other versions
JPS57527B2 (en
Inventor
Yasuo Shimizu
Yutaka Miyakoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP9653678A priority Critical patent/JPS5523576A/en
Publication of JPS5523576A publication Critical patent/JPS5523576A/en
Publication of JPS57527B2 publication Critical patent/JPS57527B2/ja
Granted legal-status Critical Current

Links

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  • Power Sources (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

PURPOSE: To prevent noise at a unit power supply or break time or a trouble time from being transmitted to the signal bus, by supplying power to drivers belonging to the unit under a condition where the power supply of the unit is established.
CONSTITUTION: When voltages P1 and P2 are established and signal S1 becomes high-level, diode D1 is cut off, and TrQ1 and Q2 are turned on, and then, relay RL1 is operated to supply power to drivers DA1 to DAn. Consequently, noise of the internal circuit which may be generated in the transitional state of voltages P1 and P2 is prevented from being transmitted to the signal bus.
COPYRIGHT: (C)1980,JPO&Japio
JP9653678A 1978-08-08 1978-08-08 Erroneous output prevention system Granted JPS5523576A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9653678A JPS5523576A (en) 1978-08-08 1978-08-08 Erroneous output prevention system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9653678A JPS5523576A (en) 1978-08-08 1978-08-08 Erroneous output prevention system

Publications (2)

Publication Number Publication Date
JPS5523576A true JPS5523576A (en) 1980-02-20
JPS57527B2 JPS57527B2 (en) 1982-01-07

Family

ID=14167831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9653678A Granted JPS5523576A (en) 1978-08-08 1978-08-08 Erroneous output prevention system

Country Status (1)

Country Link
JP (1) JPS5523576A (en)

Also Published As

Publication number Publication date
JPS57527B2 (en) 1982-01-07

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