JPS55158592A - Electronic clock - Google Patents

Electronic clock

Info

Publication number
JPS55158592A
JPS55158592A JP6584479A JP6584479A JPS55158592A JP S55158592 A JPS55158592 A JP S55158592A JP 6584479 A JP6584479 A JP 6584479A JP 6584479 A JP6584479 A JP 6584479A JP S55158592 A JPS55158592 A JP S55158592A
Authority
JP
Japan
Prior art keywords
time
down counter
circuit
timer
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6584479A
Other languages
Japanese (ja)
Inventor
Ritsu Katsuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Elemex Corp
Ricoh Co Ltd
Original Assignee
Ricoh Elemex Corp
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Elemex Corp, Ricoh Co Ltd filed Critical Ricoh Elemex Corp
Priority to JP6584479A priority Critical patent/JPS55158592A/en
Publication of JPS55158592A publication Critical patent/JPS55158592A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electric Clocks (AREA)
  • Measurement Of Predetermined Time Intervals (AREA)

Abstract

PURPOSE: To provide an electronic clock having a timer for displaying remaining time which permits informing the elapse of time at regular intervals, by furnishing the clock with an ability to preset a setting time every time the content of a down counter for use in counting the remaining time has become zero.
CONSTITUTION: A time to be set by a timer is memorized in a memory circuit 5 by switch signals input thereinto from input terminals S1, S2. When an instruction for starting the timer is given, a presetting instruction is given from a mode discriminating circuit 10 to a down counter 4 so that the down counter 4 reads as a presetting value counted data held by the memory circuit 5, to start at the same time down counting by an output pulse from a frequency dividing circuit 2. When the content of the down counter has become zero, a detector circuit 14 is actuated to give again a presetting instruction to the down counter 4. A timer data output circuit 11 is adapted to actuate an alarm 13 when it receives once a zero detected signal from the detector circuit 14.
COPYRIGHT: (C)1980,JPO&Japio
JP6584479A 1979-05-28 1979-05-28 Electronic clock Pending JPS55158592A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6584479A JPS55158592A (en) 1979-05-28 1979-05-28 Electronic clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6584479A JPS55158592A (en) 1979-05-28 1979-05-28 Electronic clock

Publications (1)

Publication Number Publication Date
JPS55158592A true JPS55158592A (en) 1980-12-10

Family

ID=13298718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6584479A Pending JPS55158592A (en) 1979-05-28 1979-05-28 Electronic clock

Country Status (1)

Country Link
JP (1) JPS55158592A (en)

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