JPS55153060A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS55153060A
JPS55153060A JP5952279A JP5952279A JPS55153060A JP S55153060 A JPS55153060 A JP S55153060A JP 5952279 A JP5952279 A JP 5952279A JP 5952279 A JP5952279 A JP 5952279A JP S55153060 A JPS55153060 A JP S55153060A
Authority
JP
Japan
Prior art keywords
arithmetic
keyboard
displayed
display unit
input information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5952279A
Other languages
Japanese (ja)
Inventor
Tomoma Tani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP5952279A priority Critical patent/JPS55153060A/en
Publication of JPS55153060A publication Critical patent/JPS55153060A/en
Pending legal-status Critical Current

Links

Landscapes

  • Calculators And Similar Devices (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To make it possible to check the operation error of a keyboard by sequentially storing input information from a keyboard operated in sequence and by reading and displaying the information after the completion of a series of arithmetic.
CONSTITUTION: Input information from keyboard 1 is supplied to arithmetic circuit 3 via XY register 2 in sequence and its arithmetic result is displayed on display unit 4 via control circuit 9. The above-mentioned input information is stored sequentially in memory circuit 5 via buffer 6. After the completion of the arithmetic, switch 8 is operated for verification, and consequently the contents of memory unit 5 are sequentially read out by reader 7 at every time of the operation and then displayed on verification display unit 10 via control circuit 9. An operator checks the error of the keyboard operation. This read information is inputted to XY register 2 at the same time and the final arithmetic result is displayed on display unit 10.
COPYRIGHT: (C)1980,JPO&Japio
JP5952279A 1979-05-15 1979-05-15 Electronic computer Pending JPS55153060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5952279A JPS55153060A (en) 1979-05-15 1979-05-15 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5952279A JPS55153060A (en) 1979-05-15 1979-05-15 Electronic computer

Publications (1)

Publication Number Publication Date
JPS55153060A true JPS55153060A (en) 1980-11-28

Family

ID=13115673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5952279A Pending JPS55153060A (en) 1979-05-15 1979-05-15 Electronic computer

Country Status (1)

Country Link
JP (1) JPS55153060A (en)

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