JPS55150053A - Fault display unit for computer - Google Patents

Fault display unit for computer

Info

Publication number
JPS55150053A
JPS55150053A JP5629679A JP5629679A JPS55150053A JP S55150053 A JPS55150053 A JP S55150053A JP 5629679 A JP5629679 A JP 5629679A JP 5629679 A JP5629679 A JP 5629679A JP S55150053 A JPS55150053 A JP S55150053A
Authority
JP
Japan
Prior art keywords
alarms
output
circuit
alarm
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5629679A
Other languages
Japanese (ja)
Inventor
Yoshiaki Obata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5629679A priority Critical patent/JPS55150053A/en
Publication of JPS55150053A publication Critical patent/JPS55150053A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To secure the restarting of a high response via the alarm combination display realy circuit possessing the on-line FF wich is set with the output of the gate circuit that supplied alarms of all necessary combinations en bloc and then delivers the output through one of those alarms.
CONSTITUTION: On-line display relay circuit 2 is controlled by the control command, and alarm display circuit 3 operates on each alarm signal. And alarm combination display relay circuit 4 is set with the start order and possesses on-line FF which is set with the output of the gate circuit that supplies the alarms of all necessary combinations en bloc and then delivers the output through one of those alarms. Thus the optional alarms are combined and then displayed to outside to secure the restarting of a high response.
COPYRIGHT: (C)1980,JPO&Japio
JP5629679A 1979-05-10 1979-05-10 Fault display unit for computer Pending JPS55150053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5629679A JPS55150053A (en) 1979-05-10 1979-05-10 Fault display unit for computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5629679A JPS55150053A (en) 1979-05-10 1979-05-10 Fault display unit for computer

Publications (1)

Publication Number Publication Date
JPS55150053A true JPS55150053A (en) 1980-11-21

Family

ID=13023142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5629679A Pending JPS55150053A (en) 1979-05-10 1979-05-10 Fault display unit for computer

Country Status (1)

Country Link
JP (1) JPS55150053A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS514385A (en) * 1974-07-02 1976-01-14 Yoshio Suzuki Nasendaijoyorikijio hakurisuruhoho

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS514385A (en) * 1974-07-02 1976-01-14 Yoshio Suzuki Nasendaijoyorikijio hakurisuruhoho

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