JPS55149549A - Channel controlling system in time sharing multiplex transmission system of bit multiplex system - Google Patents

Channel controlling system in time sharing multiplex transmission system of bit multiplex system

Info

Publication number
JPS55149549A
JPS55149549A JP5690279A JP5690279A JPS55149549A JP S55149549 A JPS55149549 A JP S55149549A JP 5690279 A JP5690279 A JP 5690279A JP 5690279 A JP5690279 A JP 5690279A JP S55149549 A JPS55149549 A JP S55149549A
Authority
JP
Japan
Prior art keywords
diagram
time sharing
multiplex
bit
sharing multiplex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5690279A
Other languages
Japanese (ja)
Inventor
Hiroshi Kokubo
Noritaka Nakano
Ryoetsu Nakajima
Kazuhisa Yoshimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5690279A priority Critical patent/JPS55149549A/en
Publication of JPS55149549A publication Critical patent/JPS55149549A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/12—Arrangements providing for calling or supervisory signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To realize the time sharing multiplex transmission system by bit multiplex system without bit delay and malfunction, by performing the identification by control information in advance based on the data information. CONSTITUTION:The time sharing multiplex unit of station itself TDM111 or MODEM13 is at sending side, then after confirming EF or DP or ON (A in the flow diagram), RS or CD is recognized (B in the diagram), and if this is ON, data delivery is made. If B in the diagram is not ON, the control code is delivered (D in the diagram). Further, RS and CD are immediately after ON or OFF, the change- over pattern consisting of all A is transmitted (E in the diagram). If the change- over pattern is transmitted in the process of assembling the procedure for TDM units, the reception side TDM unit 21 can recognize in advance the information coming next as the control code or data.
JP5690279A 1979-05-11 1979-05-11 Channel controlling system in time sharing multiplex transmission system of bit multiplex system Pending JPS55149549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5690279A JPS55149549A (en) 1979-05-11 1979-05-11 Channel controlling system in time sharing multiplex transmission system of bit multiplex system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5690279A JPS55149549A (en) 1979-05-11 1979-05-11 Channel controlling system in time sharing multiplex transmission system of bit multiplex system

Publications (1)

Publication Number Publication Date
JPS55149549A true JPS55149549A (en) 1980-11-20

Family

ID=13040375

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5690279A Pending JPS55149549A (en) 1979-05-11 1979-05-11 Channel controlling system in time sharing multiplex transmission system of bit multiplex system

Country Status (1)

Country Link
JP (1) JPS55149549A (en)

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