JPS5512531A - Memory unit - Google Patents
Memory unitInfo
- Publication number
- JPS5512531A JPS5512531A JP8387678A JP8387678A JPS5512531A JP S5512531 A JPS5512531 A JP S5512531A JP 8387678 A JP8387678 A JP 8387678A JP 8387678 A JP8387678 A JP 8387678A JP S5512531 A JPS5512531 A JP S5512531A
- Authority
- JP
- Japan
- Prior art keywords
- address
- rom
- data
- memory unit
- sum check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE:To enable to replace only the ROM element for corresponding data at data change, by providing the sum check code to only the data in the ROM element in ROM elements. CONSTITUTION:The sum check code is respectively fed to the data at 0 to 1K-2 address in 1K-1 address of ROM's 1 and 5, to the data at 1K to 2K-2 address in 2K-1 address of ROM's 2 and 6, and to the data at 2K-3K-2 in 3K-1 address of ROM's 3 and 7, and further, to the data at 3K-4K-2 address in 4K-1 address of ROM's 4 and 8. Further, at sum check, binary sum of each bit at 0 to 4K-1 address is made and chicking is made by verifying the agreement of the value to the predetermined value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8387678A JPS5512531A (en) | 1978-07-10 | 1978-07-10 | Memory unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8387678A JPS5512531A (en) | 1978-07-10 | 1978-07-10 | Memory unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5512531A true JPS5512531A (en) | 1980-01-29 |
Family
ID=13814850
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8387678A Pending JPS5512531A (en) | 1978-07-10 | 1978-07-10 | Memory unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5512531A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6455660A (en) * | 1987-08-26 | 1989-03-02 | Sanyo Electric Co | Memory circuit |
JP2009238420A (en) * | 2008-03-26 | 2009-10-15 | Tokai Rika Co Ltd | Lever switch device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4964345A (en) * | 1972-10-20 | 1974-06-21 | ||
JPS52112243A (en) * | 1976-03-17 | 1977-09-20 | Nippon Signal Co Ltd:The | Error detection system for exclusive reading memory |
-
1978
- 1978-07-10 JP JP8387678A patent/JPS5512531A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4964345A (en) * | 1972-10-20 | 1974-06-21 | ||
JPS52112243A (en) * | 1976-03-17 | 1977-09-20 | Nippon Signal Co Ltd:The | Error detection system for exclusive reading memory |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6455660A (en) * | 1987-08-26 | 1989-03-02 | Sanyo Electric Co | Memory circuit |
JP2009238420A (en) * | 2008-03-26 | 2009-10-15 | Tokai Rika Co Ltd | Lever switch device |
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