JPS5512271U - - Google Patents

Info

Publication number
JPS5512271U
JPS5512271U JP9498678U JP9498678U JPS5512271U JP S5512271 U JPS5512271 U JP S5512271U JP 9498678 U JP9498678 U JP 9498678U JP 9498678 U JP9498678 U JP 9498678U JP S5512271 U JPS5512271 U JP S5512271U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9498678U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9498678U priority Critical patent/JPS5512271U/ja
Publication of JPS5512271U publication Critical patent/JPS5512271U/ja
Pending legal-status Critical Current

Links

JP9498678U 1978-07-12 1978-07-12 Pending JPS5512271U (es)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9498678U JPS5512271U (es) 1978-07-12 1978-07-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9498678U JPS5512271U (es) 1978-07-12 1978-07-12

Publications (1)

Publication Number Publication Date
JPS5512271U true JPS5512271U (es) 1980-01-25

Family

ID=29027504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9498678U Pending JPS5512271U (es) 1978-07-12 1978-07-12

Country Status (1)

Country Link
JP (1) JPS5512271U (es)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51112282A (en) * 1975-03-07 1976-10-04 Western Electric Co Method of aligning miniature mask pattern with miniature semiconductor pattern

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51112282A (en) * 1975-03-07 1976-10-04 Western Electric Co Method of aligning miniature mask pattern with miniature semiconductor pattern

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