JPS55117319A - Signal processor - Google Patents

Signal processor

Info

Publication number
JPS55117319A
JPS55117319A JP2484379A JP2484379A JPS55117319A JP S55117319 A JPS55117319 A JP S55117319A JP 2484379 A JP2484379 A JP 2484379A JP 2484379 A JP2484379 A JP 2484379A JP S55117319 A JPS55117319 A JP S55117319A
Authority
JP
Japan
Prior art keywords
adder
supplied
digitized
level
multipliers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2484379A
Other languages
Japanese (ja)
Inventor
Ryoichi Wada
Takanori Senoo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2484379A priority Critical patent/JPS55117319A/en
Publication of JPS55117319A publication Critical patent/JPS55117319A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/002—Control of digital or coded signals

Landscapes

  • Amplifiers (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To prevent occurrence of the distortion at the low-level output time by adding the digitized noise signal after the multiplying process of the digitized audio signal. CONSTITUTION:The digitized audio signals CHA and CHB are supplied to multipliers 7 and 8 each. On the other hand, the setting position information of variable resistances VRA and VRB are supplied to level tables 5 and 6 after A/D conversions 3 and 4 each. Then the adjustment level value delivered from tables 5 and 6 are supplied to multipliers 7 and 8, and the result receives addition at adder 9. Here the output of adder 9 is added at adder 10 with the output of noise generator 11 which generates the digitized noise to be delivered as CHO after cutting down or rounding into the necessary bit number. In such way, the distortion caused by the bit cut- down process or the like at the low-level output time can be prevented.
JP2484379A 1979-03-02 1979-03-02 Signal processor Pending JPS55117319A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2484379A JPS55117319A (en) 1979-03-02 1979-03-02 Signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2484379A JPS55117319A (en) 1979-03-02 1979-03-02 Signal processor

Publications (1)

Publication Number Publication Date
JPS55117319A true JPS55117319A (en) 1980-09-09

Family

ID=12149489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2484379A Pending JPS55117319A (en) 1979-03-02 1979-03-02 Signal processor

Country Status (1)

Country Link
JP (1) JPS55117319A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62183627A (en) * 1986-02-07 1987-08-12 Sony Corp Processing system for digital data
JPH02183627A (en) * 1989-01-09 1990-07-18 Yokogawa Electric Corp D/a converter
JP2009505611A (en) * 2005-08-22 2009-02-05 フリースケール セミコンダクター インコーポレイテッド Bounded signal mixer and method of operation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62183627A (en) * 1986-02-07 1987-08-12 Sony Corp Processing system for digital data
JPH02183627A (en) * 1989-01-09 1990-07-18 Yokogawa Electric Corp D/a converter
JP2009505611A (en) * 2005-08-22 2009-02-05 フリースケール セミコンダクター インコーポレイテッド Bounded signal mixer and method of operation
JP4862045B2 (en) * 2005-08-22 2012-01-25 フリースケール セミコンダクター インコーポレイテッド Bounded signal mixer and method of operation

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