JPS55108037A - Prevention circuit for mis-interruption of serial transfer - Google Patents

Prevention circuit for mis-interruption of serial transfer

Info

Publication number
JPS55108037A
JPS55108037A JP1426879A JP1426879A JPS55108037A JP S55108037 A JPS55108037 A JP S55108037A JP 1426879 A JP1426879 A JP 1426879A JP 1426879 A JP1426879 A JP 1426879A JP S55108037 A JPS55108037 A JP S55108037A
Authority
JP
Japan
Prior art keywords
error
interruption
bit
mis
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1426879A
Other languages
Japanese (ja)
Inventor
Kazuo Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1426879A priority Critical patent/JPS55108037A/en
Publication of JPS55108037A publication Critical patent/JPS55108037A/en
Pending legal-status Critical Current

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  • Accessory Devices And Overall Control Thereof (AREA)

Abstract

PURPOSE: To prevent the occurrence of request interruption, when the selector switch of data transfer speed is set in error, by providing FF to detect whether or not the data bit after the start bit is all 0.
CONSTITUTION: It is assumed that the Baud rate switch of the typewriter 1 is set to low speed side in error and the character key is depressed. In this case, since the code making the position of the stop bit to 0 is present in the character code, framing error is outputted. But, if the bit in which the serial input SI data is changed from 0W1 before the STOP bit is present, leading signal is detected at the terminal T of FF22, request FF12 is set to 1, and the output at the terminal 0 is 0. Accordingly, the gate 11 keeps OFF, FF12 is not set. Thus, even with the operation in error, no mis-interruption is fed to the computer 3.
COPYRIGHT: (C)1980,JPO&Japio
JP1426879A 1979-02-13 1979-02-13 Prevention circuit for mis-interruption of serial transfer Pending JPS55108037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1426879A JPS55108037A (en) 1979-02-13 1979-02-13 Prevention circuit for mis-interruption of serial transfer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1426879A JPS55108037A (en) 1979-02-13 1979-02-13 Prevention circuit for mis-interruption of serial transfer

Publications (1)

Publication Number Publication Date
JPS55108037A true JPS55108037A (en) 1980-08-19

Family

ID=11856335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1426879A Pending JPS55108037A (en) 1979-02-13 1979-02-13 Prevention circuit for mis-interruption of serial transfer

Country Status (1)

Country Link
JP (1) JPS55108037A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59170933A (en) * 1983-03-17 1984-09-27 Tokyo Electric Co Ltd Input data control device of printer
JPS60112477A (en) * 1983-11-25 1985-06-18 Tokyo Electric Co Ltd Printer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59170933A (en) * 1983-03-17 1984-09-27 Tokyo Electric Co Ltd Input data control device of printer
JPH036532B2 (en) * 1983-03-17 1991-01-30 Tokyo Electric Co Ltd
JPS60112477A (en) * 1983-11-25 1985-06-18 Tokyo Electric Co Ltd Printer
JPH0351231B2 (en) * 1983-11-25 1991-08-06 Tokyo Electric Co Ltd

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