JPS55102971A - Pal-system synchronizing signal generator - Google Patents

Pal-system synchronizing signal generator

Info

Publication number
JPS55102971A
JPS55102971A JP1109879A JP1109879A JPS55102971A JP S55102971 A JPS55102971 A JP S55102971A JP 1109879 A JP1109879 A JP 1109879A JP 1109879 A JP1109879 A JP 1109879A JP S55102971 A JPS55102971 A JP S55102971A
Authority
JP
Japan
Prior art keywords
output
offset
circuit
dividing ratio
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1109879A
Other languages
Japanese (ja)
Other versions
JPS6038066B2 (en
Inventor
Takashi Nakamura
Akira Taki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP1109879A priority Critical patent/JPS6038066B2/en
Publication of JPS55102971A publication Critical patent/JPS55102971A/en
Publication of JPS6038066B2 publication Critical patent/JPS6038066B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the constitution of a circuit by making offset removal operation possible even if a decoder output or waveform-shaping output lags an original oscillation output by three clocks, by removing an offset by varying the dividing ratio of a counter.
CONSTITUTION: The original oscillation frequency of original oscillator 1 is set an integer greater than the chrominance subcarrier frequency of the PAL system and applied to counter 20 whose dividing ratio is variable; the dividing ratio is normally set to one-seventh and to one-eighth only when an offset is removed. The dividing ratio of this counter 20 is varied by the output of control circuit 22 of offset removal circuit 3 and to circuit 22, the fixed output of decoder 23 and those of waveform shaping circuits 24 and 25 based upon division outputs of horizontal and vertical periods are supplied. Then, a signal with the offset removed is applied to synthesizer 10 via PLL circuit 11 and at the output of synthesizer 10, various needed synchronizing signals appear.
COPYRIGHT: (C)1980,JPO&Japio
JP1109879A 1979-02-01 1979-02-01 PAL synchronization signal generator Expired JPS6038066B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1109879A JPS6038066B2 (en) 1979-02-01 1979-02-01 PAL synchronization signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1109879A JPS6038066B2 (en) 1979-02-01 1979-02-01 PAL synchronization signal generator

Publications (2)

Publication Number Publication Date
JPS55102971A true JPS55102971A (en) 1980-08-06
JPS6038066B2 JPS6038066B2 (en) 1985-08-29

Family

ID=11768521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1109879A Expired JPS6038066B2 (en) 1979-02-01 1979-02-01 PAL synchronization signal generator

Country Status (1)

Country Link
JP (1) JPS6038066B2 (en)

Also Published As

Publication number Publication date
JPS6038066B2 (en) 1985-08-29

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