JPS5499526A - Display device - Google Patents

Display device

Info

Publication number
JPS5499526A
JPS5499526A JP574878A JP574878A JPS5499526A JP S5499526 A JPS5499526 A JP S5499526A JP 574878 A JP574878 A JP 574878A JP 574878 A JP574878 A JP 574878A JP S5499526 A JPS5499526 A JP S5499526A
Authority
JP
Japan
Prior art keywords
data
memory
fixed
row
crt14
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP574878A
Other languages
Japanese (ja)
Inventor
Takeshi Aikawa
Takeshi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP574878A priority Critical patent/JPS5499526A/en
Publication of JPS5499526A publication Critical patent/JPS5499526A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure the high-speed and low-cost display by using the serial memory element containing the means which converts the memory data into the element fixing data via the control signal given from outside as the picture memory.
CONSTITUTION: For the memory element, the shift function to shift the data on the memory cells arrayed in series is used along with the function of the fixed memory to ganerate the fixed data which is fixed previously on the memory cells. These functions are possessed in charge transfer-type memory elements R0WRn. With these elements, the data row to be displayed on CRT14 based on clock signal 8 is shifted and held. At the same time, part of the data row is replaced with the fixed data by the data set signal given from timing generator circuit 12, and counter 9 shows the address on CRT14 for the data delivered from element Rn through counting clock signal 8. In case the data sent from the computer or the communication circuit is the graphic dot data, switch SW is connected to the a-side, and controller 7 controls the addition of the graphic dot data row to the picture memory.
COPYRIGHT: (C)1979,JPO&Japio
JP574878A 1978-01-24 1978-01-24 Display device Pending JPS5499526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP574878A JPS5499526A (en) 1978-01-24 1978-01-24 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP574878A JPS5499526A (en) 1978-01-24 1978-01-24 Display device

Publications (1)

Publication Number Publication Date
JPS5499526A true JPS5499526A (en) 1979-08-06

Family

ID=11619720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP574878A Pending JPS5499526A (en) 1978-01-24 1978-01-24 Display device

Country Status (1)

Country Link
JP (1) JPS5499526A (en)

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