JPS549519A - Balanced transmission circuit - Google Patents

Balanced transmission circuit

Info

Publication number
JPS549519A
JPS549519A JP7572277A JP7572277A JPS549519A JP S549519 A JPS549519 A JP S549519A JP 7572277 A JP7572277 A JP 7572277A JP 7572277 A JP7572277 A JP 7572277A JP S549519 A JPS549519 A JP S549519A
Authority
JP
Japan
Prior art keywords
transmission circuit
balanced transmission
package
reception
releasing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7572277A
Other languages
Japanese (ja)
Inventor
Kiyoaki Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7572277A priority Critical patent/JPS549519A/en
Publication of JPS549519A publication Critical patent/JPS549519A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/062—Setting decision thresholds using feedforward techniques only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To make it possible to fix the logical reception output at the time of releasing the sending-end, by providing the bias voltage from the transmission package to the line receiver of the reception package.
JP7572277A 1977-06-24 1977-06-24 Balanced transmission circuit Pending JPS549519A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7572277A JPS549519A (en) 1977-06-24 1977-06-24 Balanced transmission circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7572277A JPS549519A (en) 1977-06-24 1977-06-24 Balanced transmission circuit

Publications (1)

Publication Number Publication Date
JPS549519A true JPS549519A (en) 1979-01-24

Family

ID=13584432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7572277A Pending JPS549519A (en) 1977-06-24 1977-06-24 Balanced transmission circuit

Country Status (1)

Country Link
JP (1) JPS549519A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03154293A (en) * 1989-11-10 1991-07-02 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03154293A (en) * 1989-11-10 1991-07-02 Toshiba Corp Semiconductor device
JP2793296B2 (en) * 1989-11-10 1998-09-03 株式会社東芝 Semiconductor device

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