JPS5487406A - Amplitude adjusting circuit - Google Patents

Amplitude adjusting circuit

Info

Publication number
JPS5487406A
JPS5487406A JP15583477A JP15583477A JPS5487406A JP S5487406 A JPS5487406 A JP S5487406A JP 15583477 A JP15583477 A JP 15583477A JP 15583477 A JP15583477 A JP 15583477A JP S5487406 A JPS5487406 A JP S5487406A
Authority
JP
Japan
Prior art keywords
input
circuit
switch circuit
gate
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15583477A
Other languages
Japanese (ja)
Inventor
Shizuo Asano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15583477A priority Critical patent/JPS5487406A/en
Publication of JPS5487406A publication Critical patent/JPS5487406A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M7/00—Arrangements for interconnection between switching centres
    • H04M7/16—Arrangements for interconnection between switching centres in systems employing carrier frequencies

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To prevent an amplifier constituting a carrier from being appllied with an overload even if a connection confirmation signal for a switchboard (dial tone, busy tone, etc.) more than a prescribed value is inputted, by providing an amplitude adjusting circuit to the carrier. CONSTITUTION:Except during a calling time, input 1 is grounded and input 3 is in an open state. In consequence, AND gate 3 is closed, whose output makes switch circuit 1 open. The output of inverter 4, on the other hand, allows switch circuit 2 to conduct and a connection confirmation signal of more than the prescribed value from input 2 is passed through switch circuit 2 and adjusted by level adjusting circuit 5 to the prescribed level of the carrier before being sent out to the output by way of OR gate 6 and amplifier circuit 7. In the calling state, inputs 1 and 3 are both grounded and a sound talking signal from input 2 is outputted by way of switch circuit 1, OR gate 6 and amplifier circuit 7.
JP15583477A 1977-12-23 1977-12-23 Amplitude adjusting circuit Pending JPS5487406A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15583477A JPS5487406A (en) 1977-12-23 1977-12-23 Amplitude adjusting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15583477A JPS5487406A (en) 1977-12-23 1977-12-23 Amplitude adjusting circuit

Publications (1)

Publication Number Publication Date
JPS5487406A true JPS5487406A (en) 1979-07-11

Family

ID=15614508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15583477A Pending JPS5487406A (en) 1977-12-23 1977-12-23 Amplitude adjusting circuit

Country Status (1)

Country Link
JP (1) JPS5487406A (en)

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