JPS5481042A - Transmission and reception system for time information - Google Patents

Transmission and reception system for time information

Info

Publication number
JPS5481042A
JPS5481042A JP14897977A JP14897977A JPS5481042A JP S5481042 A JPS5481042 A JP S5481042A JP 14897977 A JP14897977 A JP 14897977A JP 14897977 A JP14897977 A JP 14897977A JP S5481042 A JPS5481042 A JP S5481042A
Authority
JP
Japan
Prior art keywords
control circuit
unit
count register
content
transfer instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14897977A
Other languages
Japanese (ja)
Inventor
Yuichi Narita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14897977A priority Critical patent/JPS5481042A/en
Publication of JPS5481042A publication Critical patent/JPS5481042A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable to speed up the delivery of one time for the content of real timer, for example, about 0.9 μs and to ensure the display for effectiveness.
CONSTITUTION: The real timer 5 and the control circuit 6 are provided in the outgoing unit 1, and the count register 14 and the control circuit 15 performing effective display are provided in the reception unit 2, and the control circuit 6 placed in the unit 1 delivers the transfer control searially transferred for the program unit information sectioning the content of the real timer 5 into block unit and the transfer instruction transferring the block unit information to the control circuit 15 placed in the unit 2, and the control circuit 15 instructs the effectiveness of the content of the count register 14 to the transfer instruction. Further, the count register 14 consists of shift registers and the control circuit 15 outputs shift clock to the count register 14 in synchronizing with the transfer instruction delivered from the unit 1.
COPYRIGHT: (C)1979,JPO&Japio
JP14897977A 1977-12-12 1977-12-12 Transmission and reception system for time information Pending JPS5481042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14897977A JPS5481042A (en) 1977-12-12 1977-12-12 Transmission and reception system for time information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14897977A JPS5481042A (en) 1977-12-12 1977-12-12 Transmission and reception system for time information

Publications (1)

Publication Number Publication Date
JPS5481042A true JPS5481042A (en) 1979-06-28

Family

ID=15464958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14897977A Pending JPS5481042A (en) 1977-12-12 1977-12-12 Transmission and reception system for time information

Country Status (1)

Country Link
JP (1) JPS5481042A (en)

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