JPS5480062A - Detector circuit for pulse phase difference - Google Patents

Detector circuit for pulse phase difference

Info

Publication number
JPS5480062A
JPS5480062A JP14784277A JP14784277A JPS5480062A JP S5480062 A JPS5480062 A JP S5480062A JP 14784277 A JP14784277 A JP 14784277A JP 14784277 A JP14784277 A JP 14784277A JP S5480062 A JPS5480062 A JP S5480062A
Authority
JP
Japan
Prior art keywords
pulse
phase
phase difference
terminal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14784277A
Other languages
Japanese (ja)
Inventor
Akio Tanaka
Masashi Nagano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14784277A priority Critical patent/JPS5480062A/en
Publication of JPS5480062A publication Critical patent/JPS5480062A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To secure the correct detection at all times for te relation between two pulses supplied by generating the output pulse featuring the equal pulse duration to the phase difference of the two input pulses as well as the output pulse indicating which pulse of the two features the gained phase.
CONSTITUTION: Input pulse A and B applied to input terminal 1 and 2 are processed through the input pulse process circuit comprising NAND circuit groups 3∼9 or the NOR circuit groups. This pulse process circuit possesses three terminals 20∼22: phase difference pulse C0 featuring the same duration as the phase difference between the rise of pulse A and B is deliviered at terminal 20; 1st phase relation detection pulse C1 is delivered at terminal 21 only when pulse A reatures the delayed phase to pulse B; and 2nd phase relation detection pulse C2 phase relation detection pulse C2 is delivered at terminal 22 only when pulse A features the gained phase to pulse B respectively. In this way, both the phase difference and the phase relation between the two pulses suppplied can be detected.
COPYRIGHT: (C)1979,JPO&Japio
JP14784277A 1977-12-08 1977-12-08 Detector circuit for pulse phase difference Pending JPS5480062A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14784277A JPS5480062A (en) 1977-12-08 1977-12-08 Detector circuit for pulse phase difference

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14784277A JPS5480062A (en) 1977-12-08 1977-12-08 Detector circuit for pulse phase difference

Publications (1)

Publication Number Publication Date
JPS5480062A true JPS5480062A (en) 1979-06-26

Family

ID=15439478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14784277A Pending JPS5480062A (en) 1977-12-08 1977-12-08 Detector circuit for pulse phase difference

Country Status (1)

Country Link
JP (1) JPS5480062A (en)

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