JPS5478929A - Driving system for core memory unit - Google Patents

Driving system for core memory unit

Info

Publication number
JPS5478929A
JPS5478929A JP14604577A JP14604577A JPS5478929A JP S5478929 A JPS5478929 A JP S5478929A JP 14604577 A JP14604577 A JP 14604577A JP 14604577 A JP14604577 A JP 14604577A JP S5478929 A JPS5478929 A JP S5478929A
Authority
JP
Japan
Prior art keywords
current
leading time
core
pulse
fed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14604577A
Other languages
Japanese (ja)
Inventor
Yoshiteru Nagatomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14604577A priority Critical patent/JPS5478929A/en
Publication of JPS5478929A publication Critical patent/JPS5478929A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element

Abstract

PURPOSE:To widen the operation area and to reduce the power consumption and to achieve economy, by corresponding the pulse current leading time either one of the word write-in currents to the leading time of the inhibit current and by suppressing the interferring current to the minimum. CONSTITUTION:The current waveform in the core memory in writing in the information ''O'' represents the readout currents 24a and 24b fed to the X and Y drive lines 2a to 2d and 3a to 3d through the core 1, wire-in current 25a, 31 and inhibit current 26, interference pulse current 32 subjected to the core 1, and the total readout current 27 subjective to the core selected. The reliability is increased by delaying the pulse leading time of the current 31 and matching it to the leading time of the current 26 so that the current of the current 32 is minimized, and the operation area is widened. Further, as the means delaying the pulse leading time of the current 31, the method such as the removal of the speed up capacitor 15b or the decrease of the drive voltage Vxy fed to the power supply terminal 12 is used.
JP14604577A 1977-12-07 1977-12-07 Driving system for core memory unit Pending JPS5478929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14604577A JPS5478929A (en) 1977-12-07 1977-12-07 Driving system for core memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14604577A JPS5478929A (en) 1977-12-07 1977-12-07 Driving system for core memory unit

Publications (1)

Publication Number Publication Date
JPS5478929A true JPS5478929A (en) 1979-06-23

Family

ID=15398847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14604577A Pending JPS5478929A (en) 1977-12-07 1977-12-07 Driving system for core memory unit

Country Status (1)

Country Link
JP (1) JPS5478929A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021500823A (en) * 2017-12-01 2021-01-07 天地融科技股▲ふん▼有限公司 Data transmission circuit, data reception circuit and equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021500823A (en) * 2017-12-01 2021-01-07 天地融科技股▲ふん▼有限公司 Data transmission circuit, data reception circuit and equipment

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