JPS5478034A - Fluorescent display tube dynamic display circuit - Google Patents

Fluorescent display tube dynamic display circuit

Info

Publication number
JPS5478034A
JPS5478034A JP14496977A JP14496977A JPS5478034A JP S5478034 A JPS5478034 A JP S5478034A JP 14496977 A JP14496977 A JP 14496977A JP 14496977 A JP14496977 A JP 14496977A JP S5478034 A JPS5478034 A JP S5478034A
Authority
JP
Japan
Prior art keywords
digit
inputted
counter
pulse
displaying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14496977A
Other languages
Japanese (ja)
Inventor
Naotetsu Saga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14496977A priority Critical patent/JPS5478034A/en
Publication of JPS5478034A publication Critical patent/JPS5478034A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE: To reduce comsumption power with reducing the loss current at a zero mask time by using a pulse, which has a pulse width narrower than a normal digit pulse, as a displaying digit pulse for the zero-masked digit in a display circuit.
CONSTITUTION: In the display circuit in the digital control equipment which drives a fluorescent display tube in the dynamic driving system, word wime counter 1 where word clock ϕW is inputted is provided, and the output of counter 1 is inputted to ROM to form circulating displaying digit signals W1→W2...W13→W1. Menswhile, digital clock ϕD is inputted to digital time counter 2, and the output of counter 2 is inputted to ROM to form timing signal A. Then, signal A is used as a timing signal which distributes contents of shift register 3 storing displayed data to each digit synchronously with displaying digit signals W1 to W13 and writes them into shift register 4.
COPYRIGHT: (C)1979,JPO&Japio
JP14496977A 1977-12-05 1977-12-05 Fluorescent display tube dynamic display circuit Pending JPS5478034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14496977A JPS5478034A (en) 1977-12-05 1977-12-05 Fluorescent display tube dynamic display circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14496977A JPS5478034A (en) 1977-12-05 1977-12-05 Fluorescent display tube dynamic display circuit

Publications (1)

Publication Number Publication Date
JPS5478034A true JPS5478034A (en) 1979-06-21

Family

ID=15374397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14496977A Pending JPS5478034A (en) 1977-12-05 1977-12-05 Fluorescent display tube dynamic display circuit

Country Status (1)

Country Link
JP (1) JPS5478034A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120920A (en) * 1974-03-09 1975-09-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120920A (en) * 1974-03-09 1975-09-22

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