JPS5471952A - Data processing unit - Google Patents

Data processing unit

Info

Publication number
JPS5471952A
JPS5471952A JP13863177A JP13863177A JPS5471952A JP S5471952 A JPS5471952 A JP S5471952A JP 13863177 A JP13863177 A JP 13863177A JP 13863177 A JP13863177 A JP 13863177A JP S5471952 A JPS5471952 A JP S5471952A
Authority
JP
Japan
Prior art keywords
memory
ffs
state
request
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13863177A
Other languages
Japanese (ja)
Inventor
Takeshi Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13863177A priority Critical patent/JPS5471952A/en
Publication of JPS5471952A publication Critical patent/JPS5471952A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to generate a microprogram without consideration of restrictive conditions of a main memory by controlling the memory access for the main memory dependently upon the state of FFs of a condition setting circuit and a micro instruction from a control memory.
CONSTITUTION: Main memory 5 has a page mode access function, and control memory 18 stores first memory accessing micro instructions to request a line address set and second memory accessing micro instructions to request a row address set, and further. condition setting circuit 23 has plural FFs and accepts various memory access request signals. Here, a prescribed memory access control is performed for memory 5 at a prescribed time on a basis of the state of FFs of circuit 23 and the first or the second memory accessing micro instruction read from memory 18 or the state of FFs. As a result, a microprogram can be generated without consideration of restrictive conditions of memory 5.
COPYRIGHT: (C)1979,JPO&Japio
JP13863177A 1977-11-18 1977-11-18 Data processing unit Pending JPS5471952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13863177A JPS5471952A (en) 1977-11-18 1977-11-18 Data processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13863177A JPS5471952A (en) 1977-11-18 1977-11-18 Data processing unit

Publications (1)

Publication Number Publication Date
JPS5471952A true JPS5471952A (en) 1979-06-08

Family

ID=15226558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13863177A Pending JPS5471952A (en) 1977-11-18 1977-11-18 Data processing unit

Country Status (1)

Country Link
JP (1) JPS5471952A (en)

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