JPS5471526A - Memory error monitor system - Google Patents

Memory error monitor system

Info

Publication number
JPS5471526A
JPS5471526A JP13862777A JP13862777A JPS5471526A JP S5471526 A JPS5471526 A JP S5471526A JP 13862777 A JP13862777 A JP 13862777A JP 13862777 A JP13862777 A JP 13862777A JP S5471526 A JPS5471526 A JP S5471526A
Authority
JP
Japan
Prior art keywords
error
failure
range
stop signal
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13862777A
Other languages
Japanese (ja)
Inventor
Takahiko Ogita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13862777A priority Critical patent/JPS5471526A/en
Publication of JPS5471526A publication Critical patent/JPS5471526A/en
Pending legal-status Critical Current

Links

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  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To rationally perform error logging and logout, by comparing the failure range detected in the past with that detected at present and delivering the error processing stop signal vased on the result of comparison, in the memory unit with circuit having error detection furnction.
CONSTITUTION: In the memory unit having the function detecting the faulty location of n-bit(n=1,2...), if n-bit error is taken place, the error mode decoder 12 inputting the output of comparators 4-1 to 4-4 judging the range of failure and FF9-1 to 9-4 holding the information for range of failure representing the failed information are provided. Further, the logic circuit by the OR gate with NOT gate delivering the error processing stop signal to the central processor performing suitable processing to the memory error is proveided. Then, the range of failure information at the existing error taken place and that held are compared and if the result of comparison satifies a predetermined condition, the error processing stop signal is delivered.
COPYRIGHT: (C)1979,JPO&Japio
JP13862777A 1977-11-18 1977-11-18 Memory error monitor system Pending JPS5471526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13862777A JPS5471526A (en) 1977-11-18 1977-11-18 Memory error monitor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13862777A JPS5471526A (en) 1977-11-18 1977-11-18 Memory error monitor system

Publications (1)

Publication Number Publication Date
JPS5471526A true JPS5471526A (en) 1979-06-08

Family

ID=15226472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13862777A Pending JPS5471526A (en) 1977-11-18 1977-11-18 Memory error monitor system

Country Status (1)

Country Link
JP (1) JPS5471526A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6282445A (en) * 1985-10-08 1987-04-15 Nec Corp Data error address storing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6282445A (en) * 1985-10-08 1987-04-15 Nec Corp Data error address storing device

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