JPS5470710A - Communication speed designating system - Google Patents
Communication speed designating systemInfo
- Publication number
- JPS5470710A JPS5470710A JP13812577A JP13812577A JPS5470710A JP S5470710 A JPS5470710 A JP S5470710A JP 13812577 A JP13812577 A JP 13812577A JP 13812577 A JP13812577 A JP 13812577A JP S5470710 A JPS5470710 A JP S5470710A
- Authority
- JP
- Japan
- Prior art keywords
- communication speed
- circuit
- signal
- communication
- speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0262—Arrangements for detecting the data rate of an incoming signal
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To secure an automatic detection of the communication speed at the reception side for the data communication by transmitting one character for the designated communication speed at the transmission side at the communication start time. CONSTITUTION:When circuit RD becomes ''O'', the start of the circuit use is shown. And signal (a) is delivered through start detection circuit 1, and then an optional character which contains one bit at the head is transmitted from the transmission side. The 1-bit length is detected through mark monitor circuit 2 and bit length monitor circuit 3. Then clock signal (c) is counted by counter 6 for the time from rise of signal (b) to the rise of signal (d), and this count value (e) is used as the designation speed for the communication speed. The relationship between value (e) and the communication speed is decided by setting the clock period of memory circuit 5.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13812577A JPS5470710A (en) | 1977-11-17 | 1977-11-17 | Communication speed designating system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13812577A JPS5470710A (en) | 1977-11-17 | 1977-11-17 | Communication speed designating system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5470710A true JPS5470710A (en) | 1979-06-06 |
Family
ID=15214546
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13812577A Pending JPS5470710A (en) | 1977-11-17 | 1977-11-17 | Communication speed designating system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5470710A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56106460A (en) * | 1980-01-16 | 1981-08-24 | Bosch Gmbh Robert | Data transmitter |
JPS61140258A (en) * | 1984-12-13 | 1986-06-27 | Casio Comput Co Ltd | Baud rate automatic decision system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5072503A (en) * | 1973-10-29 | 1975-06-16 |
-
1977
- 1977-11-17 JP JP13812577A patent/JPS5470710A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5072503A (en) * | 1973-10-29 | 1975-06-16 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56106460A (en) * | 1980-01-16 | 1981-08-24 | Bosch Gmbh Robert | Data transmitter |
JPS61140258A (en) * | 1984-12-13 | 1986-06-27 | Casio Comput Co Ltd | Baud rate automatic decision system |
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