JPS547067Y2 - - Google Patents
Info
- Publication number
- JPS547067Y2 JPS547067Y2 JP4282672U JP4282672U JPS547067Y2 JP S547067 Y2 JPS547067 Y2 JP S547067Y2 JP 4282672 U JP4282672 U JP 4282672U JP 4282672 U JP4282672 U JP 4282672U JP S547067 Y2 JPS547067 Y2 JP S547067Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Mounting Of Printed Circuit Boards And The Like (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4282672U JPS547067Y2 (en:Method) | 1972-04-11 | 1972-04-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4282672U JPS547067Y2 (en:Method) | 1972-04-11 | 1972-04-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS494160U JPS494160U (en:Method) | 1974-01-14 |
| JPS547067Y2 true JPS547067Y2 (en:Method) | 1979-04-03 |
Family
ID=27916017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4282672U Expired JPS547067Y2 (en:Method) | 1972-04-11 | 1972-04-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS547067Y2 (en:Method) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5551208B2 (en:Method) * | 1972-12-02 | 1980-12-23 |
-
1972
- 1972-04-11 JP JP4282672U patent/JPS547067Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS494160U (en:Method) | 1974-01-14 |