JPS5466038A - Display unit - Google Patents

Display unit

Info

Publication number
JPS5466038A
JPS5466038A JP13251277A JP13251277A JPS5466038A JP S5466038 A JPS5466038 A JP S5466038A JP 13251277 A JP13251277 A JP 13251277A JP 13251277 A JP13251277 A JP 13251277A JP S5466038 A JPS5466038 A JP S5466038A
Authority
JP
Japan
Prior art keywords
circuit
inputted
signal
clock
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13251277A
Other languages
Japanese (ja)
Inventor
Yasufumi Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13251277A priority Critical patent/JPS5466038A/en
Publication of JPS5466038A publication Critical patent/JPS5466038A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate the application of a high voltage to an electrode, and to prevent the deterioration in life of the electrode and its burning, by providing an external clock supervisory circuit and internal clock generating circuit and by operating the internal clock circuit while the external clock circuit is stopping.
CONSTITUTION: External clock signal 8 is inputted to supervisory circuit 2, whose output is inputted to AND circuit 4 of control circuit 20. The other output of supervisory circuit 2 is inputted to AND circuit 5 together with clock signal 9 from internal clock generating circuit 3, and outputs of AND circuits 4 and 5 are inputted to OR circuit 6, whose output is inputted as clock signal 12 to display part 7. When detecting the stop of external signal 8, supervisory circuit 2 sends out control signal 11, which is AND-ed by AND circuit 5 with internal signal 9 of internal generating circuit 3 to output clock signal 12, thereby operating display part 7 positively. Consequently, the continuous application of a high voltage to the electrode can be prevented.
COPYRIGHT: (C)1979,JPO&Japio
JP13251277A 1977-11-07 1977-11-07 Display unit Pending JPS5466038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13251277A JPS5466038A (en) 1977-11-07 1977-11-07 Display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13251277A JPS5466038A (en) 1977-11-07 1977-11-07 Display unit

Publications (1)

Publication Number Publication Date
JPS5466038A true JPS5466038A (en) 1979-05-28

Family

ID=15083065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13251277A Pending JPS5466038A (en) 1977-11-07 1977-11-07 Display unit

Country Status (1)

Country Link
JP (1) JPS5466038A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002297108A (en) * 2001-03-30 2002-10-11 Hitachi Ltd Liquid crystal display device and driving method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50159917A (en) * 1974-06-13 1975-12-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50159917A (en) * 1974-06-13 1975-12-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002297108A (en) * 2001-03-30 2002-10-11 Hitachi Ltd Liquid crystal display device and driving method thereof

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