JPS5460528A - Multiple virtual memory control equipment - Google Patents
Multiple virtual memory control equipmentInfo
- Publication number
- JPS5460528A JPS5460528A JP12682577A JP12682577A JPS5460528A JP S5460528 A JPS5460528 A JP S5460528A JP 12682577 A JP12682577 A JP 12682577A JP 12682577 A JP12682577 A JP 12682577A JP S5460528 A JPS5460528 A JP S5460528A
- Authority
- JP
- Japan
- Prior art keywords
- virtual space
- purge
- stack
- action
- frequencies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To reduce the overhead caused by the virtual space purge by reducing the frequencies of the cancel action, i.e., the virtual space purge action of the high- speed address conversion device via switching of the unit virtual space.
CONSTITUTION: The number of the virtual space number is set so that it may be an integer-multiplication of the register number forming stack 4. At first, the virtual space of a certain unit which is registered in high-speed address conversion device 7 is purged at one time only when the enlarged integer-multiplied virtual space number is overflowed. After this, the singal is delivered to purge indication line 102 every time four units of new STO (segment table origin address ) are stored in stack 4 to carry out the purge action. Thus, the frequencies of the virtual space purge can be reduced without lowering the effective use of stack 4
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12682577A JPS5460528A (en) | 1977-10-24 | 1977-10-24 | Multiple virtual memory control equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12682577A JPS5460528A (en) | 1977-10-24 | 1977-10-24 | Multiple virtual memory control equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5460528A true JPS5460528A (en) | 1979-05-16 |
JPS5652387B2 JPS5652387B2 (en) | 1981-12-11 |
Family
ID=14944855
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12682577A Granted JPS5460528A (en) | 1977-10-24 | 1977-10-24 | Multiple virtual memory control equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5460528A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5644180A (en) * | 1979-09-17 | 1981-04-23 | Nec Corp | Information retrieval device |
JP2010134956A (en) * | 2004-02-06 | 2010-06-17 | Intel Corp | Address conversion technique in context switching environment |
-
1977
- 1977-10-24 JP JP12682577A patent/JPS5460528A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5644180A (en) * | 1979-09-17 | 1981-04-23 | Nec Corp | Information retrieval device |
JP2010134956A (en) * | 2004-02-06 | 2010-06-17 | Intel Corp | Address conversion technique in context switching environment |
Also Published As
Publication number | Publication date |
---|---|
JPS5652387B2 (en) | 1981-12-11 |
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