JPS5446587A - Data input device for electronic counter - Google Patents

Data input device for electronic counter

Info

Publication number
JPS5446587A
JPS5446587A JP11303377A JP11303377A JPS5446587A JP S5446587 A JPS5446587 A JP S5446587A JP 11303377 A JP11303377 A JP 11303377A JP 11303377 A JP11303377 A JP 11303377A JP S5446587 A JPS5446587 A JP S5446587A
Authority
JP
Japan
Prior art keywords
clocks
signals
circuit
supplied
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11303377A
Other languages
Japanese (ja)
Inventor
Yoshitaka Ogino
Masao Hosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP11303377A priority Critical patent/JPS5446587A/en
Publication of JPS5446587A publication Critical patent/JPS5446587A/en
Pending legal-status Critical Current

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  • Arrangements For Transmission Of Measured Signals (AREA)

Abstract

PURPOSE: To simplify the circuit by impressing the up-down counting signals, which are generated when a maual switch is turned on, and carry signals upon a counter which is supplied with clocks as all times.
CONSTITUTION: When one of UP and DOWN switches is turned on, UP or DOWN signals are generated so that an FF 1 is set through overflow preventing gate 4 or 5. And, counters 21 and 22, which are supplied with the clocks of an oscillator 3 at all times, are brought into UP or DOWN mode. At the same time, the carry signals from the logic circuit 6, which is supplied with the UP and DOWN signals through the gates 4 and 5, are impressed so that the counters 21 and 22 effect the UP or DOWN count of the clocks of the oscillator 3. According to such construction, the clocks are impressed no indirectly through the gate circuit but directly to a counter so that the circuit can be so cimplified as to be free from any miscount due to the influences from the impedance of the connecting wire
COPYRIGHT: (C)1979,JPO&Japio
JP11303377A 1977-09-20 1977-09-20 Data input device for electronic counter Pending JPS5446587A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11303377A JPS5446587A (en) 1977-09-20 1977-09-20 Data input device for electronic counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11303377A JPS5446587A (en) 1977-09-20 1977-09-20 Data input device for electronic counter

Publications (1)

Publication Number Publication Date
JPS5446587A true JPS5446587A (en) 1979-04-12

Family

ID=14601763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11303377A Pending JPS5446587A (en) 1977-09-20 1977-09-20 Data input device for electronic counter

Country Status (1)

Country Link
JP (1) JPS5446587A (en)

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