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Publication date
Application filedfiledCritical
Priority to JP1975037040UpriorityCriticalpatent/JPS5430937Y2/ja
Publication of JPS51118053UpublicationCriticalpatent/JPS51118053U/ja
Application grantedgrantedCritical
Publication of JPS5430937Y2publicationCriticalpatent/JPS5430937Y2/ja
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
H01L2224/42—Wire connectors; Manufacturing methods related thereto
H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
H01L2224/4805—Shape
H01L2224/4809—Loop shape
H01L2224/48091—Arched
H—ELECTRICITY
H01—ELECTRIC ELEMENTS
H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
H01L2924/191—Disposition
H01L2924/19101—Disposition of discrete passive components
H01L2924/19107—Disposition of discrete passive components off-chip wires