JPS5427221B2 - - Google Patents
Info
- Publication number
- JPS5427221B2 JPS5427221B2 JP8191975A JP8191975A JPS5427221B2 JP S5427221 B2 JPS5427221 B2 JP S5427221B2 JP 8191975 A JP8191975 A JP 8191975A JP 8191975 A JP8191975 A JP 8191975A JP S5427221 B2 JPS5427221 B2 JP S5427221B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/001—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
- Logic Circuits (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Read Only Memory (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50081919A JPS526044A (en) | 1975-07-04 | 1975-07-04 | Dynamic decoder circuit |
US05/701,125 US4027174A (en) | 1975-07-04 | 1976-06-30 | Dynamic decoder circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50081919A JPS526044A (en) | 1975-07-04 | 1975-07-04 | Dynamic decoder circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS526044A JPS526044A (en) | 1977-01-18 |
JPS5427221B2 true JPS5427221B2 (cs) | 1979-09-08 |
Family
ID=13759851
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50081919A Granted JPS526044A (en) | 1975-07-04 | 1975-07-04 | Dynamic decoder circuit |
Country Status (2)
Country | Link |
---|---|
US (1) | US4027174A (cs) |
JP (1) | JPS526044A (cs) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0346326B2 (cs) * | 1985-06-10 | 1991-07-15 | Nissan Shatai Co | |
JPH0346325B2 (cs) * | 1985-06-10 | 1991-07-15 | Nissan Shatai Co |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2641693C2 (de) * | 1976-09-16 | 1978-11-16 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Decodierschaltung mit MOS-Transistoren |
US4194130A (en) * | 1977-11-21 | 1980-03-18 | Motorola, Inc. | Digital predecoding system |
JPS6023432B2 (ja) * | 1977-12-09 | 1985-06-07 | 株式会社日立製作所 | Mosメモリ |
JPS5641579A (en) * | 1979-09-10 | 1981-04-18 | Toshiba Corp | Address selector |
JPS5925846U (ja) * | 1982-08-04 | 1984-02-17 | 小川 修身 | 電源遮断装置付き放送用受信機 |
JPS5991054U (ja) * | 1982-12-09 | 1984-06-20 | 日本マランツ株式会社 | 放送波によるオ−トパワ−オフ回路 |
US4514829A (en) * | 1982-12-30 | 1985-04-30 | International Business Machines Corporation | Word line decoder and driver circuits for high density semiconductor memory |
JPS6075126A (ja) * | 1983-09-30 | 1985-04-27 | Nec Corp | 多入力論理回路 |
ATE79977T1 (de) * | 1987-06-10 | 1992-09-15 | Siemens Ag | Schaltungsanordnung in einer integrierten halbleiterschaltung. |
JP2550684B2 (ja) * | 1988-11-04 | 1996-11-06 | 日本電気株式会社 | 半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3644904A (en) * | 1969-11-12 | 1972-02-22 | Gen Instrument Corp | Chip select circuit for multichip random access memory |
US3717868A (en) * | 1970-07-27 | 1973-02-20 | Texas Instruments Inc | Mos memory decode |
US3786437A (en) * | 1972-01-03 | 1974-01-15 | Honeywell Inf Systems | Random access memory system utilizing an inverting cell concept |
US3778784A (en) * | 1972-02-14 | 1973-12-11 | Intel Corp | Memory system incorporating a memory cell and timing means on a single semiconductor substrate |
US3848237A (en) * | 1973-02-20 | 1974-11-12 | Advanced Memory Syst | High speed mos random access read/write memory device |
US3900742A (en) * | 1974-06-24 | 1975-08-19 | Us Navy | Threshold logic using complementary mos device |
US3959781A (en) * | 1974-11-04 | 1976-05-25 | Intel Corporation | Semiconductor random access memory |
-
1975
- 1975-07-04 JP JP50081919A patent/JPS526044A/ja active Granted
-
1976
- 1976-06-30 US US05/701,125 patent/US4027174A/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0346326B2 (cs) * | 1985-06-10 | 1991-07-15 | Nissan Shatai Co | |
JPH0346325B2 (cs) * | 1985-06-10 | 1991-07-15 | Nissan Shatai Co |
Also Published As
Publication number | Publication date |
---|---|
JPS526044A (en) | 1977-01-18 |
US4027174A (en) | 1977-05-31 |