JPS54159124A - Clock forming circuit in synchronizing with burst signal - Google Patents

Clock forming circuit in synchronizing with burst signal

Info

Publication number
JPS54159124A
JPS54159124A JP6854078A JP6854078A JPS54159124A JP S54159124 A JPS54159124 A JP S54159124A JP 6854078 A JP6854078 A JP 6854078A JP 6854078 A JP6854078 A JP 6854078A JP S54159124 A JPS54159124 A JP S54159124A
Authority
JP
Japan
Prior art keywords
signal
synchronizing
frequency
burst signal
difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6854078A
Other languages
Japanese (ja)
Other versions
JPS6011517B2 (en
Inventor
Kiyoshi Sawagata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP53068540A priority Critical patent/JPS6011517B2/en
Publication of JPS54159124A publication Critical patent/JPS54159124A/en
Publication of JPS6011517B2 publication Critical patent/JPS6011517B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To develop the clocks in synchronizing with the burst signal, by detecting the frequency signal of the difference between the clock output in synchronizing with the burst signal and the signal N times the horizontal synchronizing frequency and controlling the oscillator so that the frequency having a given difference can be obtained with the output.
CONSTITUTION: The start stop type oscillator 7 obtaines the clock in synchronizing with the burst signal started with the burst signal, and it is inputted to the multiplier 11 together with the output signal having the frequency N times the horizontal synchronising signal form the signal forming circuit 8, and the signal having the frequency for the difference of the both input frequencies is outputted. Further, this signal is detected 13, and the oscillation frequency of the oscillator 7 is controlled so that the freqyency difference can be constant based on the detected output. Thus, with a simple constitution, the clock in synchronizing with the burst signal can be obtained.
COPYRIGHT: (C)1979,JPO&Japio
JP53068540A 1978-06-07 1978-06-07 Clock formation circuit synchronized with burst signal Expired JPS6011517B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53068540A JPS6011517B2 (en) 1978-06-07 1978-06-07 Clock formation circuit synchronized with burst signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53068540A JPS6011517B2 (en) 1978-06-07 1978-06-07 Clock formation circuit synchronized with burst signal

Publications (2)

Publication Number Publication Date
JPS54159124A true JPS54159124A (en) 1979-12-15
JPS6011517B2 JPS6011517B2 (en) 1985-03-26

Family

ID=13376670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53068540A Expired JPS6011517B2 (en) 1978-06-07 1978-06-07 Clock formation circuit synchronized with burst signal

Country Status (1)

Country Link
JP (1) JPS6011517B2 (en)

Also Published As

Publication number Publication date
JPS6011517B2 (en) 1985-03-26

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