JPS54152835A - Program error correcting device - Google Patents

Program error correcting device

Info

Publication number
JPS54152835A
JPS54152835A JP6185778A JP6185778A JPS54152835A JP S54152835 A JPS54152835 A JP S54152835A JP 6185778 A JP6185778 A JP 6185778A JP 6185778 A JP6185778 A JP 6185778A JP S54152835 A JPS54152835 A JP S54152835A
Authority
JP
Japan
Prior art keywords
interruption
execution
program
debug
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6185778A
Other languages
Japanese (ja)
Inventor
Yoshimi Suzuki
Tetsuo Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6185778A priority Critical patent/JPS54152835A/en
Publication of JPS54152835A publication Critical patent/JPS54152835A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To increase the debug efficiency by providing the interruption signal generator circuit to produce the interruption signals with optional intervals.
CONSTITUTION: Interruption signal generator circuit 4 produces the interruption signals with fixed intervals to host machine 1 based on the clocks when the address is within a fixed range. For execution of program A at machine 1, interruption signal 6 is produced based on the timing of clock 5 when the address is within the set range after comparison 3 with preset 7 value via address signal line 2, and execution of A proceeds to program B to be restarted after execution of B. All processes mentioned above are carried out through machine 1, and accordingly both the debug software and hardware means can be used as in the case of the single program. Furthermore, the production timing can be changed freely for the interruption signal by varying the clock 5 and the set value of setting circuit 7. Thus, the debug is possible in consideration of various kinds of interruption signals.
COPYRIGHT: (C)1979,JPO&Japio
JP6185778A 1978-05-23 1978-05-23 Program error correcting device Pending JPS54152835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6185778A JPS54152835A (en) 1978-05-23 1978-05-23 Program error correcting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6185778A JPS54152835A (en) 1978-05-23 1978-05-23 Program error correcting device

Publications (1)

Publication Number Publication Date
JPS54152835A true JPS54152835A (en) 1979-12-01

Family

ID=13183183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6185778A Pending JPS54152835A (en) 1978-05-23 1978-05-23 Program error correcting device

Country Status (1)

Country Link
JP (1) JPS54152835A (en)

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