JPS54152817A - Automatic clear circuit - Google Patents

Automatic clear circuit

Info

Publication number
JPS54152817A
JPS54152817A JP6106078A JP6106078A JPS54152817A JP S54152817 A JPS54152817 A JP S54152817A JP 6106078 A JP6106078 A JP 6106078A JP 6106078 A JP6106078 A JP 6106078A JP S54152817 A JPS54152817 A JP S54152817A
Authority
JP
Japan
Prior art keywords
circuit
output
clear operation
clear
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6106078A
Other languages
Japanese (ja)
Inventor
Haruo Keida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6106078A priority Critical patent/JPS54152817A/en
Publication of JPS54152817A publication Critical patent/JPS54152817A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To secure the assured automatic clear operation by actuating the time constant circuit which secures the time necessary for the automatic clear operation after the power voltage rises higher than the minimum operation voltage of the electronic circuit and delivering the clear signals during the operation period.
CONSTITUTION: The detection output of voltage detector circuit 1 features the low level for the level under which both power voltage VGG and VDD turn on MISFETQ8 and Q9, thus the low-level clear operation signals being delivered. When both VGG and VDD feature the voltage enough to turn on MISFETQ8 and Q9, the output of circuit 1 becomes the high level turn on MISFETQ13 and then to actuate time constant circuit 2. Then the time necessary for the clear operation is set up by the time constant (C1, Q14), and thus the assured clear operation is ensured under the rise of any power voltage. After this, the output of circuit 2 is applied to FF circuit 3, and the output is inverted to the high level to release the clear operation but with the output kept inverse. Thus, the automatic clear circuit can be applied widely.
COPYRIGHT: (C)1979,JPO&Japio
JP6106078A 1978-05-24 1978-05-24 Automatic clear circuit Pending JPS54152817A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6106078A JPS54152817A (en) 1978-05-24 1978-05-24 Automatic clear circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6106078A JPS54152817A (en) 1978-05-24 1978-05-24 Automatic clear circuit

Publications (1)

Publication Number Publication Date
JPS54152817A true JPS54152817A (en) 1979-12-01

Family

ID=13160243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6106078A Pending JPS54152817A (en) 1978-05-24 1978-05-24 Automatic clear circuit

Country Status (1)

Country Link
JP (1) JPS54152817A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331209A (en) * 1992-02-28 1994-07-19 Oki Electric Industry Co., Ltd. Auto-reset circuit with improved testability

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331209A (en) * 1992-02-28 1994-07-19 Oki Electric Industry Co., Ltd. Auto-reset circuit with improved testability

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