JPS54148342A - Reset control system for terminal unit in information process system - Google Patents

Reset control system for terminal unit in information process system

Info

Publication number
JPS54148342A
JPS54148342A JP5651778A JP5651778A JPS54148342A JP S54148342 A JPS54148342 A JP S54148342A JP 5651778 A JP5651778 A JP 5651778A JP 5651778 A JP5651778 A JP 5651778A JP S54148342 A JPS54148342 A JP S54148342A
Authority
JP
Japan
Prior art keywords
reset
making time
carried out
time
normal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5651778A
Other languages
Japanese (ja)
Other versions
JPS5824811B2 (en
Inventor
Ryoichi Okuyama
Susumu Suzuki
Toshiyuki Tanaka
Takaaki Hatano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53056517A priority Critical patent/JPS5824811B2/en
Publication of JPS54148342A publication Critical patent/JPS54148342A/en
Publication of JPS5824811B2 publication Critical patent/JPS5824811B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To carry out the all-clear of the table area plus the request and reception of the table only at the making time of the power supply by deciding whether the reset at the power making time or the normal reset based on the program.
CONSTITUTION: When the power supply reset or the normal reset occurs at terminal units 31-1W31-n, the parity check is carried out for the table through parity check circuit 24 and based on address designation 23. And if some error is detected then, the power making time is decided. Thus, the table area of RAM23 is all cleared, and at the same time the WBCC breakdown is carried out. Then the table WBCC checking is carried out, and then the application is given when it is the normal resetting time. On the oter hand, the table request is given at the power making time, and terminal control part 30 is driven. Thus, the tables are collected from corresponding terminal units 31-1W31-n and then sent to RAM23 where the internal table is renewed to the data. As a result, the processing capacity is increased greatly for the microprocessor system.
COPYRIGHT: (C)1979,JPO&Japio
JP53056517A 1978-05-15 1978-05-15 Reset control method for terminal devices in information processing systems Expired JPS5824811B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53056517A JPS5824811B2 (en) 1978-05-15 1978-05-15 Reset control method for terminal devices in information processing systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53056517A JPS5824811B2 (en) 1978-05-15 1978-05-15 Reset control method for terminal devices in information processing systems

Publications (2)

Publication Number Publication Date
JPS54148342A true JPS54148342A (en) 1979-11-20
JPS5824811B2 JPS5824811B2 (en) 1983-05-24

Family

ID=13029305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53056517A Expired JPS5824811B2 (en) 1978-05-15 1978-05-15 Reset control method for terminal devices in information processing systems

Country Status (1)

Country Link
JP (1) JPS5824811B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5779535A (en) * 1980-11-06 1982-05-18 Canon Inc Information processor
JPS58169219A (en) * 1982-03-31 1983-10-05 Nec Home Electronics Ltd Memory contents holding system of microcomputer
JPS6074009A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Decision system for flag in initialization
JPS6188317A (en) * 1984-10-05 1986-05-06 Seiko Epson Corp Distinction method of power-on and reset
JPS61139844A (en) * 1984-12-12 1986-06-27 Minolta Camera Co Ltd Microprocessor built-in device
JPS621036A (en) * 1985-04-10 1987-01-07 マイクロソフト　コ−ポレ−シヨン Execution of program for multimode microprocessor and operating system
JPH08110824A (en) * 1995-04-24 1996-04-30 Seiko Epson Corp Information processor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3831148A (en) * 1973-01-02 1974-08-20 Honeywell Inf Systems Nonexecute test apparatus
JPS532051A (en) * 1976-06-28 1978-01-10 Fujitsu Ltd Program load system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3831148A (en) * 1973-01-02 1974-08-20 Honeywell Inf Systems Nonexecute test apparatus
JPS532051A (en) * 1976-06-28 1978-01-10 Fujitsu Ltd Program load system

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5779535A (en) * 1980-11-06 1982-05-18 Canon Inc Information processor
JPS58169219A (en) * 1982-03-31 1983-10-05 Nec Home Electronics Ltd Memory contents holding system of microcomputer
JPS6074009A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Decision system for flag in initialization
JPH0442684B2 (en) * 1983-09-30 1992-07-14 Fujitsu Ltd
JPS6188317A (en) * 1984-10-05 1986-05-06 Seiko Epson Corp Distinction method of power-on and reset
JPS61139844A (en) * 1984-12-12 1986-06-27 Minolta Camera Co Ltd Microprocessor built-in device
JPS621036A (en) * 1985-04-10 1987-01-07 マイクロソフト　コ−ポレ−シヨン Execution of program for multimode microprocessor and operating system
JPH08110824A (en) * 1995-04-24 1996-04-30 Seiko Epson Corp Information processor

Also Published As

Publication number Publication date
JPS5824811B2 (en) 1983-05-24

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