JPS54147394A - Speed controller for moving device - Google Patents

Speed controller for moving device

Info

Publication number
JPS54147394A
JPS54147394A JP5475678A JP5475678A JPS54147394A JP S54147394 A JPS54147394 A JP S54147394A JP 5475678 A JP5475678 A JP 5475678A JP 5475678 A JP5475678 A JP 5475678A JP S54147394 A JPS54147394 A JP S54147394A
Authority
JP
Japan
Prior art keywords
counter
speed instruction
speed
subtraction
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5475678A
Other languages
Japanese (ja)
Inventor
Yoshifumi Ito
Yoshitomo Takizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5475678A priority Critical patent/JPS54147394A/en
Publication of JPS54147394A publication Critical patent/JPS54147394A/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Velocity Or Acceleration (AREA)

Abstract

PURPOSE: To optionally alter the control pattern of a speed instruction voltage in a speed controller for a moving device by so providing a speed instruction voltage as to optionally set the increasing or decreasing detrimental operating time from predetermined value.
CONSTITUTION: The binary output f of an addition and subtraction counter 1 for setting the speed of a moving machine is converted to a decimal speed instruction value v by a decoder 3. A time data potentiometer 4 sets the time date responsive to the speed instruction value v to preset subtraction counter 5. When the time set in the counter 5 is elapsed, a timing control circuit 7 produces a pulse q to the counter 1 as an addition and subtraction pulse. The binary output f of the counter 1 is converted to an analog value by a DA converter 2, and outputted as a speed instruction voltage e.
COPYRIGHT: (C)1979,JPO&Japio
JP5475678A 1978-05-09 1978-05-09 Speed controller for moving device Pending JPS54147394A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5475678A JPS54147394A (en) 1978-05-09 1978-05-09 Speed controller for moving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5475678A JPS54147394A (en) 1978-05-09 1978-05-09 Speed controller for moving device

Publications (1)

Publication Number Publication Date
JPS54147394A true JPS54147394A (en) 1979-11-17

Family

ID=12979611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5475678A Pending JPS54147394A (en) 1978-05-09 1978-05-09 Speed controller for moving device

Country Status (1)

Country Link
JP (1) JPS54147394A (en)

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