JPS5414601A - Channel selector - Google Patents
Channel selectorInfo
- Publication number
- JPS5414601A JPS5414601A JP8080877A JP8080877A JPS5414601A JP S5414601 A JPS5414601 A JP S5414601A JP 8080877 A JP8080877 A JP 8080877A JP 8080877 A JP8080877 A JP 8080877A JP S5414601 A JPS5414601 A JP S5414601A
- Authority
- JP
- Japan
- Prior art keywords
- channel selector
- opeation
- disturbing
- mos
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
PURPOSE: To enable correct opeation without disturbing the content of memory, by setting the power supply between the MOS-IC and the non-volatile semiconductor memory element memorizing the channel selection digital signal to a given timing.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8080877A JPS5414601A (en) | 1977-07-05 | 1977-07-05 | Channel selector |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8080877A JPS5414601A (en) | 1977-07-05 | 1977-07-05 | Channel selector |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5414601A true JPS5414601A (en) | 1979-02-03 |
JPS5745091B2 JPS5745091B2 (en) | 1982-09-25 |
Family
ID=13728757
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8080877A Granted JPS5414601A (en) | 1977-07-05 | 1977-07-05 | Channel selector |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5414601A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5490936A (en) * | 1977-12-28 | 1979-07-19 | Toshiba Corp | Refresh unit for non-volatile memory |
JPH06329484A (en) * | 1993-05-20 | 1994-11-29 | Seiji Mizuno | Technique for decorating tile |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5276844A (en) * | 1975-12-23 | 1977-06-28 | Fujitsu Ltd | Initialization of memory |
-
1977
- 1977-07-05 JP JP8080877A patent/JPS5414601A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5276844A (en) * | 1975-12-23 | 1977-06-28 | Fujitsu Ltd | Initialization of memory |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5490936A (en) * | 1977-12-28 | 1979-07-19 | Toshiba Corp | Refresh unit for non-volatile memory |
JPH06329484A (en) * | 1993-05-20 | 1994-11-29 | Seiji Mizuno | Technique for decorating tile |
JPH07100637B2 (en) * | 1993-05-20 | 1995-11-01 | 清司 水野 | Tile decoration technique |
Also Published As
Publication number | Publication date |
---|---|
JPS5745091B2 (en) | 1982-09-25 |
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