JPS5414447B2 - - Google Patents
Info
- Publication number
- JPS5414447B2 JPS5414447B2 JP12358475A JP12358475A JPS5414447B2 JP S5414447 B2 JPS5414447 B2 JP S5414447B2 JP 12358475 A JP12358475 A JP 12358475A JP 12358475 A JP12358475 A JP 12358475A JP S5414447 B2 JPS5414447 B2 JP S5414447B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Superheterodyne Receivers (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Transceivers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50123584A JPS5247315A (en) | 1975-10-14 | 1975-10-14 | Phase lock loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50123584A JPS5247315A (en) | 1975-10-14 | 1975-10-14 | Phase lock loop circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5247315A JPS5247315A (en) | 1977-04-15 |
| JPS5414447B2 true JPS5414447B2 (cs) | 1979-06-07 |
Family
ID=14864196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50123584A Granted JPS5247315A (en) | 1975-10-14 | 1975-10-14 | Phase lock loop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5247315A (cs) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5599851A (en) * | 1979-01-24 | 1980-07-30 | Hitachi Ltd | Mobile data reception system |
-
1975
- 1975-10-14 JP JP50123584A patent/JPS5247315A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5247315A (en) | 1977-04-15 |