JPS54137257A - Automatic transaction device - Google Patents

Automatic transaction device

Info

Publication number
JPS54137257A
JPS54137257A JP4553978A JP4553978A JPS54137257A JP S54137257 A JPS54137257 A JP S54137257A JP 4553978 A JP4553978 A JP 4553978A JP 4553978 A JP4553978 A JP 4553978A JP S54137257 A JPS54137257 A JP S54137257A
Authority
JP
Japan
Prior art keywords
mode
signal
deposit
time
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4553978A
Other languages
Japanese (ja)
Inventor
Katsuyuki Tokura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4553978A priority Critical patent/JPS54137257A/en
Publication of JPS54137257A publication Critical patent/JPS54137257A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To avoid execution for the inhibited transaction mode as well as to secure a display for the executable mode by providing a timer within the automatic deposit draw-out machine in order to secure an automatic switch to the transaction mode at the preset time.
CONSTITUTION: Oscillator 9 generates the clock pulse, and clock 5 counts the pulses to produce time signal S1 and S2. These signals are supplied to time setting board 7 and 8. Board 7 is used for the deposit mode and delivers set signal S3 of FF10 coinciding to the start time and reset signal S4 at the stop time respectively. Board 8 is used for the payment mode and also delivers set and reset signals S5 and S6. The Q-output of FF10 and 11 becomes 1 by signal S3 and S5, and AND gate 12 and 13 are opened. On the other hand, the Q-output is applied to amplifier 14 and 15 to turn on lamp 16 and 17 to display that the operation mode is executable. When the user pushed deposit selector button 18, the high-level signal is supplied to control unit 6 via gate 13 to execute the program. The Q-output of FF10 becomes O at the deposit end time to turn off lamp 16 and to close gate 13.
COPYRIGHT: (C)1979,JPO&Japio
JP4553978A 1978-04-18 1978-04-18 Automatic transaction device Pending JPS54137257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4553978A JPS54137257A (en) 1978-04-18 1978-04-18 Automatic transaction device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4553978A JPS54137257A (en) 1978-04-18 1978-04-18 Automatic transaction device

Publications (1)

Publication Number Publication Date
JPS54137257A true JPS54137257A (en) 1979-10-24

Family

ID=12722171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4553978A Pending JPS54137257A (en) 1978-04-18 1978-04-18 Automatic transaction device

Country Status (1)

Country Link
JP (1) JPS54137257A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5287098A (en) * 1976-09-28 1977-07-20 Toshiba Corp Automatic receiving and paying apparatus
JPS52129256A (en) * 1976-04-22 1977-10-29 Sharp Corp Electronic cash register
JPS5319291B2 (en) * 1973-10-13 1978-06-20

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5319291B2 (en) * 1973-10-13 1978-06-20
JPS52129256A (en) * 1976-04-22 1977-10-29 Sharp Corp Electronic cash register
JPS5287098A (en) * 1976-09-28 1977-07-20 Toshiba Corp Automatic receiving and paying apparatus

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