JPS54134940A - Communication controller - Google Patents

Communication controller

Info

Publication number
JPS54134940A
JPS54134940A JP4215878A JP4215878A JPS54134940A JP S54134940 A JPS54134940 A JP S54134940A JP 4215878 A JP4215878 A JP 4215878A JP 4215878 A JP4215878 A JP 4215878A JP S54134940 A JPS54134940 A JP S54134940A
Authority
JP
Japan
Prior art keywords
circuit
controller
decoder
rom
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4215878A
Other languages
Japanese (ja)
Inventor
Kenji Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4215878A priority Critical patent/JPS54134940A/en
Publication of JPS54134940A publication Critical patent/JPS54134940A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE: To obtain a simplified communication controller with generality, by enabling this controller to serve as a parity generator and a decoder or a parity check circuit and a decoder by a ROM.
CONSTITUTION: In the transmission-side circuit, transmitting data stored temporarily in buffer 1 are converted by shift register 5 into serial data, which are outputted to a communication circuit via connection circuit 6. In the reception- side circuit, on the other hand, signals from the communication circuit are received by connection circuit 7 and then converted by shift register 8 into parallel data, which are retained temporarily in buffer 9. Then, either ROM 13 or 14 finds a control code in the received data and adds or makes a check a parity bit, so that either controller 2 or 12 will be actuated by the discriminated code.
COPYRIGHT: (C)1979,JPO&Japio
JP4215878A 1978-04-12 1978-04-12 Communication controller Pending JPS54134940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4215878A JPS54134940A (en) 1978-04-12 1978-04-12 Communication controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4215878A JPS54134940A (en) 1978-04-12 1978-04-12 Communication controller

Publications (1)

Publication Number Publication Date
JPS54134940A true JPS54134940A (en) 1979-10-19

Family

ID=12628134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4215878A Pending JPS54134940A (en) 1978-04-12 1978-04-12 Communication controller

Country Status (1)

Country Link
JP (1) JPS54134940A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4879552A (en) * 1972-01-24 1973-10-25
JPS50159938A (en) * 1974-06-14 1975-12-24

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4879552A (en) * 1972-01-24 1973-10-25
JPS50159938A (en) * 1974-06-14 1975-12-24

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