JPS54125558U - - Google Patents
Info
- Publication number
- JPS54125558U JPS54125558U JP2075278U JP2075278U JPS54125558U JP S54125558 U JPS54125558 U JP S54125558U JP 2075278 U JP2075278 U JP 2075278U JP 2075278 U JP2075278 U JP 2075278U JP S54125558 U JPS54125558 U JP S54125558U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2075278U JPS54125558U (en) | 1978-02-22 | 1978-02-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2075278U JPS54125558U (en) | 1978-02-22 | 1978-02-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS54125558U true JPS54125558U (en) | 1979-09-01 |
Family
ID=28852320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2075278U Pending JPS54125558U (en) | 1978-02-22 | 1978-02-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54125558U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002543732A (en) * | 1999-04-30 | 2002-12-17 | モーセッド・テクノロジーズ・インコーポレイテッド | Frequency multiplication delay lock loop |
| JP2008035544A (en) * | 2007-09-13 | 2008-02-14 | Mitsubishi Electric Corp | Pulse generating circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3586884A (en) * | 1968-01-25 | 1971-06-22 | Int Standard Electric Corp | Circuit to control the duration of pulses |
-
1978
- 1978-02-22 JP JP2075278U patent/JPS54125558U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3586884A (en) * | 1968-01-25 | 1971-06-22 | Int Standard Electric Corp | Circuit to control the duration of pulses |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002543732A (en) * | 1999-04-30 | 2002-12-17 | モーセッド・テクノロジーズ・インコーポレイテッド | Frequency multiplication delay lock loop |
| JP2010074859A (en) * | 1999-04-30 | 2010-04-02 | Mosaid Technol Inc | Frequency-multiplying circuit |
| JP4619446B2 (en) * | 1999-04-30 | 2011-01-26 | モーセッド・テクノロジーズ・インコーポレイテッド | Frequency multiplier circuit |
| JP2008035544A (en) * | 2007-09-13 | 2008-02-14 | Mitsubishi Electric Corp | Pulse generating circuit |