JPS54116587A - Sequence controller - Google Patents

Sequence controller

Info

Publication number
JPS54116587A
JPS54116587A JP2319778A JP2319778A JPS54116587A JP S54116587 A JPS54116587 A JP S54116587A JP 2319778 A JP2319778 A JP 2319778A JP 2319778 A JP2319778 A JP 2319778A JP S54116587 A JPS54116587 A JP S54116587A
Authority
JP
Japan
Prior art keywords
sequence controller
circuit
prom
prom writer
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2319778A
Other languages
Japanese (ja)
Inventor
Takeshi Terauchi
Hideji Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP2319778A priority Critical patent/JPS54116587A/en
Publication of JPS54116587A publication Critical patent/JPS54116587A/en
Pending legal-status Critical Current

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  • Programmable Controllers (AREA)

Abstract

PURPOSE:To promote a simplification of he device, by having the system's CPUs for common use, with the PROM writer constituted into a board shape and enabled to be installed to the sequence controller, in the PROM writer provided sequence controller. CONSTITUTION:On a substrate 6 constituting a PROM writer B, are mounted a memory (ROM)8, in which a PROM rewriting control program is stored, a writing control circuit 9, for processing a writing on the basis of said program, a RAM address setting switch group S4, and so on, with a freely detachable installation made capable to a sequence controller A. On the other hand, in the sequence controller A, are provided a CPU12, I/F circuit 13, 14 PROM15, for storing the control program of an objective equipment 17, and a work area (RAM)16, for temporarily storing various data generated as the control advances, with an operational panel 5 connected to an I/F circuit 13.
JP2319778A 1978-03-01 1978-03-01 Sequence controller Pending JPS54116587A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2319778A JPS54116587A (en) 1978-03-01 1978-03-01 Sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2319778A JPS54116587A (en) 1978-03-01 1978-03-01 Sequence controller

Publications (1)

Publication Number Publication Date
JPS54116587A true JPS54116587A (en) 1979-09-10

Family

ID=12103935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2319778A Pending JPS54116587A (en) 1978-03-01 1978-03-01 Sequence controller

Country Status (1)

Country Link
JP (1) JPS54116587A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58158706A (en) * 1982-03-13 1983-09-21 Matsushita Electric Works Ltd Sequence controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58158706A (en) * 1982-03-13 1983-09-21 Matsushita Electric Works Ltd Sequence controller

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