JPS54111766A - Coupling construction of lead and heat sink in semiconductor device - Google Patents

Coupling construction of lead and heat sink in semiconductor device

Info

Publication number
JPS54111766A
JPS54111766A JP1844778A JP1844778A JPS54111766A JP S54111766 A JPS54111766 A JP S54111766A JP 1844778 A JP1844778 A JP 1844778A JP 1844778 A JP1844778 A JP 1844778A JP S54111766 A JPS54111766 A JP S54111766A
Authority
JP
Japan
Prior art keywords
heat sink
lead
semiconductor device
coupling
coupling construction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1844778A
Other languages
Japanese (ja)
Inventor
Hajime Sato
Susumu Okikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1844778A priority Critical patent/JPS54111766A/en
Publication of JPS54111766A publication Critical patent/JPS54111766A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To incorporate the lead and the heat sink, by pressing the lead groove to the groove provided on the heat sink.
CONSTITUTION: The groove 0.3 to 0.7 μm thick is provided on the heat sink as the lead end, and the lead end is fixed with pressing or fastening. In the heat sink made of copper, the coupling is made at a high temperature to use the thermal contract of copper, then the mechanical strength after fixing is great. With this method, the coupling of the heat sink and the lead can be done with fine space having the width of lead end and the heat sink can be made small in size.
COPYRIGHT: (C)1979,JPO&Japio
JP1844778A 1978-02-22 1978-02-22 Coupling construction of lead and heat sink in semiconductor device Pending JPS54111766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1844778A JPS54111766A (en) 1978-02-22 1978-02-22 Coupling construction of lead and heat sink in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1844778A JPS54111766A (en) 1978-02-22 1978-02-22 Coupling construction of lead and heat sink in semiconductor device

Publications (1)

Publication Number Publication Date
JPS54111766A true JPS54111766A (en) 1979-09-01

Family

ID=11971868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1844778A Pending JPS54111766A (en) 1978-02-22 1978-02-22 Coupling construction of lead and heat sink in semiconductor device

Country Status (1)

Country Link
JP (1) JPS54111766A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503452A (en) * 1981-05-18 1985-03-05 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method for manufacturing the same
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
JP2013201169A (en) * 2012-03-23 2013-10-03 Renesas Electronics Corp Semiconductor device and manufacturing method of the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5115854B2 (en) * 1972-02-03 1976-05-20
JPS5242067B2 (en) * 1972-05-19 1977-10-21

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5115854B2 (en) * 1972-02-03 1976-05-20
JPS5242067B2 (en) * 1972-05-19 1977-10-21

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503452A (en) * 1981-05-18 1985-03-05 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method for manufacturing the same
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
JP2013201169A (en) * 2012-03-23 2013-10-03 Renesas Electronics Corp Semiconductor device and manufacturing method of the same
US9230831B2 (en) 2012-03-23 2016-01-05 Renesas Electronics Corporation Semiconductor device and a manufacturing method thereof
US9396971B2 (en) 2012-03-23 2016-07-19 Renesas Electronics Corporation Semiconductor device and a manufacturing method thereof

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