JPS54108564A - Adding-subtracting counter circuit - Google Patents
Adding-subtracting counter circuitInfo
- Publication number
- JPS54108564A JPS54108564A JP1572478A JP1572478A JPS54108564A JP S54108564 A JPS54108564 A JP S54108564A JP 1572478 A JP1572478 A JP 1572478A JP 1572478 A JP1572478 A JP 1572478A JP S54108564 A JPS54108564 A JP S54108564A
- Authority
- JP
- Japan
- Prior art keywords
- input
- subtraction
- addition
- circuit
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
Landscapes
- Measurement Of Radiation (AREA)
Abstract
PURPOSE:To improve serviceableness by obtaining [-1], [-2]... as counting contents when a subtraction input arrives with the counting contents [0], by making subtraction by an addition input and by making addition by a subtraction input when [-] is displayed. CONSTITUTION:When a subtraction input arrives from counting output [+4], [+3], [+2], [+1], [000], [-1], [-] are outputted as counting contents. Namely, while [-] display unit 42 is operating, the output of NAND circuit 14 is ''H'', that of NOR circuit 21 is ''L'', and that of NOT circuit 32 is ''H''. Therefore, NOR circuits 23 and 24 are ON and NOR circuits 22 and 25 are OFF; and an addition input is transmitted to the down input terminal of up-down counter 41 by way of NAND circuit 12, and NOR circuits 24 and 27, and a subtraction input is to the up input terminal by way of NOT circuit 34 and NOR circuits 23 and 26. Namely, subtraction is made by the addition input, and addition by the subtraction input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1572478A JPS54108564A (en) | 1978-02-14 | 1978-02-14 | Adding-subtracting counter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1572478A JPS54108564A (en) | 1978-02-14 | 1978-02-14 | Adding-subtracting counter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS54108564A true JPS54108564A (en) | 1979-08-25 |
Family
ID=11896697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1572478A Pending JPS54108564A (en) | 1978-02-14 | 1978-02-14 | Adding-subtracting counter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54108564A (en) |
-
1978
- 1978-02-14 JP JP1572478A patent/JPS54108564A/en active Pending
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