JPS54106104A - Control signal receiving circuit - Google Patents

Control signal receiving circuit

Info

Publication number
JPS54106104A
JPS54106104A JP1310878A JP1310878A JPS54106104A JP S54106104 A JPS54106104 A JP S54106104A JP 1310878 A JP1310878 A JP 1310878A JP 1310878 A JP1310878 A JP 1310878A JP S54106104 A JPS54106104 A JP S54106104A
Authority
JP
Japan
Prior art keywords
control signal
output
input level
detector
reception
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1310878A
Other languages
Japanese (ja)
Inventor
Tsuneaki Oka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1310878A priority Critical patent/JPS54106104A/en
Publication of JPS54106104A publication Critical patent/JPS54106104A/en
Pending legal-status Critical Current

Links

Landscapes

  • Mobile Radio Communication Systems (AREA)
  • Selective Calling Equipment (AREA)

Abstract

PURPOSE: To prevent the unsteady sequence ralation of the logic caused by the obscure time information of the control signal and thus to eliminate the malfunction and to secure the steady control action, by controlling the reception detecting velocity of the control signal in accordance with the reception input level.
CONSTITUTION: The arrival signal caught by antenna 11 is demodulated via receiver 12, and the control signal is selected by BPF13 and then amplified through amplifier 14. The amplified control signal is rectified through rectifier 15 to be applied to adder 16. On the other hand, part of the demodulated output of receiver 12 is applied to input level detector 18 to detect the input level, and the output which detected the input level is applied to adder 16 to control the response velocity of the output of rectifier 15 which selects the control signal in response to the output of detector 18. In other examples of application, gain control signal generator 20 is provided to detector 18 output to generate the gain control signal according to the reception level detection output. With this control signal, the gain of amplifier 14 is controlled.
COPYRIGHT: (C)1979,JPO&Japio
JP1310878A 1978-02-08 1978-02-08 Control signal receiving circuit Pending JPS54106104A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1310878A JPS54106104A (en) 1978-02-08 1978-02-08 Control signal receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1310878A JPS54106104A (en) 1978-02-08 1978-02-08 Control signal receiving circuit

Publications (1)

Publication Number Publication Date
JPS54106104A true JPS54106104A (en) 1979-08-20

Family

ID=11823945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1310878A Pending JPS54106104A (en) 1978-02-08 1978-02-08 Control signal receiving circuit

Country Status (1)

Country Link
JP (1) JPS54106104A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0238843U (en) * 1988-09-07 1990-03-15

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0238843U (en) * 1988-09-07 1990-03-15
JPH087715Y2 (en) * 1988-09-07 1996-03-04 京セラ株式会社 Cordless telephone device

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