JPS54104731A - Ghost reducing unit - Google Patents
Ghost reducing unitInfo
- Publication number
- JPS54104731A JPS54104731A JP1167678A JP1167678A JPS54104731A JP S54104731 A JPS54104731 A JP S54104731A JP 1167678 A JP1167678 A JP 1167678A JP 1167678 A JP1167678 A JP 1167678A JP S54104731 A JPS54104731 A JP S54104731A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- circuits
- output
- amplitude
- polarity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moirĂ© or halo
- H04N5/211—Ghost signal cancellation
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Noise Elimination (AREA)
- Picture Signal Circuits (AREA)
Abstract
PURPOSE:To reduce the ghost accurately, by providing two units providing variable delay circuit, differentiating circuit, amplitude and polarity conversion circuit, phase detection circuit, and DC conversion circuit, and by adjusting the amplitude and polarity of signal automatically. CONSTITUTION:The variable delay circuit 2 delaying composite video signal and the amplitude and polarity adjusting circuit 3 adjusting the amplitude and the polarity of the output of the circuit 2 are provided, and further, the delay circuit 4 delaying the output of the circuit 2, the amplitude and polarity adjusting circuit 5 adjusting the amplitude and the polarity of the output of the circuit 4, and the synthesis circuit 1 synthesizing the output of the circuits 5 and 3 with the composite video signal at the input terminal 1, are provided. Futher, the differentiating circuit 6 differentiating the output of the circuit 1, and the differentiating circuits 10 and 7 differentiating the output of the circuits 4 and 2 respectively, are provided, and also, the phase detection circuits 11 and 8 inputting the differentiated output of the circuits 10,6 and 10 and 7 respectively and performing phase detection, and the DC conversion circuits 12 and 9 converting the output of the circuits 11 and 8 into DC, are provided, controlling the circuits 3 and 5 with the output of the circuits 12 and 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1167678A JPS54104731A (en) | 1978-02-03 | 1978-02-03 | Ghost reducing unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1167678A JPS54104731A (en) | 1978-02-03 | 1978-02-03 | Ghost reducing unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54104731A true JPS54104731A (en) | 1979-08-17 |
Family
ID=11784588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1167678A Pending JPS54104731A (en) | 1978-02-03 | 1978-02-03 | Ghost reducing unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54104731A (en) |
-
1978
- 1978-02-03 JP JP1167678A patent/JPS54104731A/en active Pending
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